High-Performance InGaAs HEMTs on Si Substrates for RF Applications

In this paper, we have fabricated InGaAs high-electron-mobility transistors (HEMTs) on Si substrates. The InAlAs/InGaAs heterostructures were initially grown on InP substrates by molecular beam epitaxy (MBE), and the adhesive wafer bonding technique was employed to bond the InP substrates to Si substrates, thereby forming high-quality InGaAs channel on Si. The 120 nm gate length device shows a maximum drain current (ID,max) of 569 mA/mm, and the maximum extrinsic transconductance (gm,max) of 1112 mS/mm. The current gain cutoff frequency (fT) is as high as 273 GHz and the maximum oscillation frequency (fMAX) reaches 290 GHz. To the best of our knowledge, the gm,max and the fT of our device are the highest ever reported in InGaAs channel HEMTs on Si substrates at given gate length above 100 nm.

InP and InGaAs grown on InP substrate by molecular beam epitaxy

InP and InGaAs epitaxial layers on InP substrates using molecular beam epitaxy (MBE) have been studied. Carrier concentration and mobility of InP and InGaAs are found that are strongly correlated with the growth temperature and V/III ratio. The InGaAs layers using As2 were compared with the layers grown using As4 from a Riber standard cracker cell. When As4 is used, the highest electron mobility of InGaAs is 3960 cm2/(V·s) with the V/III ratio of 65. When converted to As2, the V/III ratio with the highest electron mobility decreased to 20. With the arsenic cracker temperature decreased from 950 ℃ to 830 ℃, the electron mobility increased from 4090 cm2/(V • s) to 5060 cm2/(V • s).

Nanoscale wafer patterning using SPM induced local anodic oxidation in InP substrates

Scanning probe microscopy assisted local anodic oxidation offers advantages over other semiconductor fabrication techniques as it is a low contamination method. We demonstrate the fabrication of deep and highly reproducible nanohole arrays on InP using local anodic oxidation. Nanohole and nano-oxide mound radius and depth are controlled independently by altering atomic force microscope tip bias and humidity, with a maximum nanohole depth of 15.6 ± 1.2 nm being achieved. Additionally, the effect of tip write speed on oxide line formation is compared for n-type, p-type and semi-insulating substrates, which shows that n-type InP oxidises at a slower rate that semi-insulated or p-type InP. Finally, we calculate the activation energy for LAO of semi-insulating InP to be 0.4 eV, suggesting the oxidation mechanism is similar to that which occurs during plasma oxidation.

Growing epitaxial layers of InP/InGaAsP heterostructures on the profiled InP surfaces by liquid-phase epitaxy

The effect of various planes was studied when growing epitaxial layers by liquid-phase epitaxy (LPE) on the profiled InP substrates. The studies allowed obtaining buried heterostructures in the InP/InGaAsP system and creating highly efficient laser diodes and image sensors.It was found that protruding mesa strips or in-depth mesa strips in the form of channels formed by the {111}А, {111}B, {110}, {112}A, or {221}A family of planes can be obtained with the corresponding selection of an etching agent, strip orientation, and a method of obtaining a masking coating. It was noted that in the case of the polarity of axes being in the direction of <111>, the cut of mesa strips was conducted along the most densely packaged planes. This cut led to the difference in rates of both chemical etching and epitaxial burying of profiled surfaces.The cut was made along the planes at a low dissolution rate {111}A for a sphalerite lattice, to which the studied material, indium phosphide, belongs. Analysis of planes {110} and {Ī10} showed that the location of the most densely packaged planes {111}A and {111}B relative to them is different.