Modeling a Chilean Hospital Using Specification and Description Language

In this chapter, the authors present a formal model of the Anesthesia Unit and Surgical Wards (UAPQ) of a Chilean hospital. The objective was to document and to understand its operation, to assist hospital management and to facilitate its simulation. The model was built with Specification and Description Language (SDL). This methodology was used because it allows the design of a model that represents the system in a graphical, modular, and standard way. Our design contains the following agents: the system, 11 blocks, and 52 processes. The blocks and the processes describe the clinical and administrative activities. The environment of the UAPQ model contains 3 components: clinical services, emergency units, and support units.

Model-Based System Design Using SysML

Model-based system design is served by a single, multi-layered model supporting all design activities, in different levels of detail. SysML is a modeling language, endorsed by OMG, for system engineering, which aims at defining such models for system design. It provides discrete diagrams to describe system structure and components, to explore allocation policies crucial for system design, and to identify design requirements. In this chapter, SysML is used for the model-based design of enterprise information system architecture, supporting a systemic view of such systems, where software and hardware entities are treated as system components composed to create the system architecture. SysML extensions to facilitate the effective description of non-functional requirements, especially quantitative ones, and their verification are presented. The integration of evaluation parameters and results into a discrete SysML diagram enhances the requirement verification process, while the visualization of evaluation data helps system engineers to explore design decisions and properly adjust system design. Based on the proposed extensions, a SysML profile is developed. The experience obtained when applying the profile for renovating the architecture of a large-scale enterprise information system is also briefly discussed to explore the potential of the proposed extensions.

The DEVS Formalism

The DEVS formalism is a set of conventions introduced in 1976 for the specification of discrete event simulation models. This chapter explains the core concepts of DEVS by applying the formalism to a single ongoing example. First, the example is introduced as a set of informal requirements from which a formal specification is to be developed. Readers are then presented with alternative sets of modeling conventions which, lacking the DEVS formalism’s approach to representing state, prove inadequate for the example. The chapter exploits the DEVS formalism’s support for modular model design, as the system in the example is specified first in parts and later as a combination of those parts. The concept of legitimacy is demonstrated on various model specifications, and the relationship between DEVS and both object-oriented programming and parallel computing is discussed.

Agent-Based Simulation Model Representation Using BPMN

Conceptual modelling is the process of abstracting a model from a real or proposed system into a conceptual model. An explicit conceptual model representation allows the model to be communicated and analysed by the stakeholders involved in a simulation project. A good representation that can be understood by all stakeholders is especially essential when the project involves different stakeholders. The three commonly used paradigms in business applications are discrete-event simulation, agent-based simulation, and system dynamics. While the conceptual model representations in discrete-event simulation and system dynamics have been dominated by process-flow and stock-and-flow diagrams, respectively, research into the conceptual model representation in agent-based simulation is relatively new. Many existing representation methods for agent-based simulation models are less friendly to business users. This chapter advocates the use of Business Process Model and Notation (BPMN) diagrams for the agent-based simulation conceptual model representation in the context of business applications. This chapter also demonstrates how the proposed BPMN representation and other methods such as Petri Nets, DEVS, and UML are used to represent the well-known SugarScape model.

Domain Specific Simulation Modeling with SysML and Model-to-Model Transformation for Discrete Processes

In this chapter, the authors present an approach for developing a simulation-tool-independent description of manufacturing systems and how to convert such a general model into simulation-tool-specific models. They show why we need standards for these discrete processes, what the state of the art is, why SysML has the chance to become a standard in modeling discrete systems, and how to use it. The authors present SysML and explain how to model discrete systems with it. For that, they explain the concept of domain-specific modeling in detail. They furthermore have a look at model-to-model transformations and its validation and verification. Finally, the authors examine different SysML modeling tools and how to improve the usability of SysML tools for engineers.

Conceptual Modeling Using Petri Nets

Petri nets are used by our students as a formal modeling technique before building a working simulation model in Arena or Simio. The Petri net model enables the simulation analyst to build a complete, unambiguous, and readable model of the target process before coding it in the target simulation tool. One of the aims of this chapter is to emphasize the need for formal specification of the simulation model before it is coded in the chosen target simulation environment. Formal specification of the model is of great help throughout the simulation project life cycle, especially in the coding and verification phase.

An Integrated Framework to Simulate SysML Models Using DEVS Simulators

System models validation is an important engineering activity of the system development life-cycle, usually performed via simulation. However, usability and effectiveness of many validation approaches are hindered by the fact that system simulation is not performed using a system model described by a standardized modeling language as SysML. This requires system simulation models to be recreated from scratch, burdening the engineer and introducing inconsistencies between system and validation models. In this chapter, the authors present how system engineers may effectively perform SysML system model validation utilizing the original SysML model and standards-based simulated related extensions. This is achieved by a framework that exploits MDA concepts and techniques, such as profiling, meta-modeling, and formal transformations. This way an open, standards-based, customizable approach for SysML models validation using DEVS simulators is formed. A simple battle system is used as an example throughout the chapter to facilitate the presentation of the proposed approach.

Formal Consistency Verification of UML Requirement and Analysis Models

To capture and analyze the functional requirements of an information system, UML and the Unified Process (UP) propose the use case and sequence diagrams. However, one of the main difficulties behind the use of UML is how to ensure the consistency of the various diagrams used to model different views of the same system. In this chapter, the authors propose an enriched format for documenting UML2.0 use cases. This format facilitates consistency verification of the functional requirements with respect to the sequence diagrams included in the analysis model. The consistency verification relies on a set of rules to check the correspondence among the elements of the documented use cases and those of the sequence diagrams; the correspondence exploits the implicit semantic relationship between these diagrams as defined in UP. Furthermore, to provide for a rigorous verification, the authors formalize both types of diagrams and their correspondence rules in the formal notation Z. The formal version of the analysis model is then verified through the theorem prover Z/EVES to ensure its consistency.

Specification and Description Language for Discrete Simulation

Designing a new simulation model usually involves the participation of personnel with different knowledge of the system and with diverse formations. These personnel often use different languages, making more difficult the task to define the existing relations between the key model elements. These relations represent the hypotheses that constrain the model and the global behavior of the system, and this information must be obtained from the system experts. A formalism can be a powerful tool to understand the model complexity and helps in the communication between the different actors that participate in the definition of the model. In this chapter we review the use of the “Specification and Description Language,” a standard and graphical language that simplifies the model understanding thanks to its modular nature. To do this we present a complete example, representing a simple queuing model that helps the reader to understand the structure and the nature of the language.

Thermal Analysis of the MIPS Processor Formulated within DEVS Conventions

The MIPS processor is used in computer architecture courses in order to explain matters such as performance analysis, energy consumption, and reliability. Currently, due to the desire for more powerful computers, it is interesting to learn how to reallocate certain components in order to achieve heat reduction with low cooling costs. DEVS is a general formalism for modeling and analysis of discrete event systems based on set theory and represents a basis for discrete event abstractions by formalizing the concept of activity which relates to the specification and heterogeneous distribution of events in space and time. The MIPS simulator is built upon known techniques for discrete event simulation and its definition within a formal language such as DEVS provides completeness, verifiability, extensibility, and maintainability. In this chapter, the authors carry out a thermal analysis of the MIPS processor using a DEVS simulator and show a register reallocation policy based on evolutionary algorithms that notably decreases the resulting register bank temperature.