Wafer-Level Three-Dimensional Hyper-Integration Technology Using Dielectric Adhesive Wafer Bonding

ABSTRACTWafer level monolithic three-dimensional (3D) integration is an emerging technology to realize enhanced performance and functionality with reduced form-factor and manufacturing cost. The cornerstone for this 3D processing technology is full-wafer bonding under back-end-of-the-line (BEOL) compatible process conditions. For the first time to our knowledge, we demonstrate nearly void-free 200 mm wafer-to-wafer bonding with an ultra-thin Ti adhesive coating, annealed at BEOL-compatible temperature (400 °C) in vacuum with external pressure applied. Mechanical integrity test showed that bonded wafer pair survived after a stringent three-step thinning process (grinding/polishing/wet-etching) with complete removal of top Si wafer, while allowing optical inspection of bonding interface. Mechanisms contributing to the strong bonding at Ti/Si interface are briefly discussed.

Download Full-text

Wafer-Level 3D Integration Based on Poly (Diallyl Phthalate) Adhesive Bonding

Micromachines ◽

10.3390/mi12121586 ◽

2021 ◽

Vol 12 (12) ◽

pp. 1586

Author(s):

Zhong Fang ◽

Peng You ◽

Yijie Jia ◽

Xuchao Pan ◽

Yunlei Shi ◽

...

Keyword(s):

Adhesive Bonding ◽

Low Cost ◽

Three Dimensional ◽

System Level ◽

Process Conditions ◽

Wafer Level ◽

3D Integration ◽

Bonding Pressure ◽

Curing Conditions ◽

Integration Technology

Three-dimensional integration technology provides a promising total solution that can be used to achieve system-level integration with high function density and low cost. In this study, a wafer-level 3D integration technology using PDAP as an intermediate bonding polymer was applied effectively for integration with an SOI wafer and dummy a CMOS wafer. The influences of the procedure parameters on the adhesive bonding effects were determined by Si–Glass adhesive bonding tests. It was found that the bonding pressure, pre-curing conditions, spin coating conditions, and cleanliness have a significant influence on the bonding results. The optimal procedure parameters for PDAP adhesive bonding were obtained through analysis and comparison. The 3D integration tests were conducted according to these optimal parameters. In the tests, process optimization was focused on Si handle-layer etching, PDAP layer etching, and Au pillar electroplating. After that, the optimal process conditions for the 3D integration process were achieved. The 3D integration applications of the micro-bolometer array and the micro-bridge resistor array were presented. It was confirmed that 3D integration based on PDAP adhesive bonding is suitable for the fabrication of system-on-chip when using MEMS and IC integration and that it is especially useful for the fabrication of low-cost suspended-microstructure on-CMOS-chip systems.

Download Full-text

New Three-Dimensional Integration Technology Based on Reconfigured Wafer-on-Wafer Bonding Technique

2007 IEEE International Electron Devices Meeting ◽

10.1109/iedm.2007.4419119 ◽

2007 ◽

Cited By ~ 64

Author(s):

Takafumi Fukushima ◽

Hirokazu Kikuchi ◽

Yusuke Yamada ◽

Takayuki Konno ◽

Jun Liang ◽

...

Keyword(s):

Wafer Bonding ◽

Three Dimensional ◽

Integration Technology ◽

Bonding Technique

Download Full-text

Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections

IEEE Transactions on Electron Devices ◽

10.1109/ted.2006.884079 ◽

2006 ◽

Vol 53 (11) ◽

pp. 2799-2808 ◽

Cited By ~ 182

Author(s):

M. Koyanagi ◽

T. Nakamura ◽

Y. Yamada ◽

H. Kikuchi ◽

T. Fukushima ◽

...

Keyword(s):

Wafer Bonding ◽

Three Dimensional ◽

Integration Technology

Download Full-text

New Three-Dimensional Integration Technology Using Chip-to-Wafer Bonding to Achieve Ultimate Super-Chip Integration

Japanese Journal of Applied Physics ◽

10.1143/jjap.45.3030 ◽

2006 ◽

Vol 45 (4B) ◽

pp. 3030-3035 ◽

Cited By ~ 45

Author(s):

Takafumi Fukushima ◽

Yusuke Yamada ◽

Hirokazu Kikuchi ◽

Mitsumasa Koyanagi

Keyword(s):

Wafer Bonding ◽

Three Dimensional ◽

Integration Technology

Download Full-text

Mechanisms of Low-Temperature Ti/Si-Based Wafer Bonding

MRS Proceedings ◽

10.1557/proc-863-b10.7 ◽

2005 ◽

Vol 863 ◽

Cited By ~ 1

Author(s):

Jian Yu ◽

Yinmin Wang ◽

Arthur W. Haberl ◽

Hassa Bakhru ◽

Jian-Qiang Lu ◽

...

Keyword(s):

Silicon Wafer ◽

Wafer Bonding ◽

Rutherford Backscattering Spectrometry ◽

Three Dimensional ◽

Amorphous Layer ◽

Bonding Interface ◽

Native Oxide ◽

Wafer Level ◽

Transmission Electron ◽

Strong Adhesion

AbstractThree-dimensional (3D) wafer-level integration is receiving increased attention with various wafer bonding approaches being evaluated. Recently, we explored an alternative lowtemperature Ti/Si-based wafer bonding, in which an oxidized silicon wafer was successfully bonded with a prime silicon wafer at 400°C using 30 nm sputtered Ti as adhesive. The bonded pairs show excellent bonding uniformity and mechanical integrity. Rutherford backscattering spectrometry (RBS) was applied to confirm the interdiffusion occurred in the interlayer. The bonding interface was examined by high-resolution transmission electron microscopy (HRTEM) assisted with electron energy loss spectroscopy (EELS) elemental mapping and energy dispersive X-ray spectroscopy (EDX). Characterization of the bonding interface indicates the strong adhesion achieved is attributed to an amorphous layer formed by interdiffusion of Si and oxygen into Ti interlayer and the unique ability to reduce native oxide (SiO2) by Ti even at low temperatures.

Download Full-text

Planarization Issues in Wafer-Level Three-Dimensional (3D) Integration

MRS Proceedings ◽

10.1557/proc-816-k7.7 ◽

2004 ◽

Vol 816 ◽

Cited By ~ 4

Author(s):

J.-Q. Lu ◽

G. Rajagopalan ◽

M. Gupta ◽

T.S. Cale ◽

R.J. Gutmann

Keyword(s):

Wafer Bonding ◽

Three Dimensional ◽

Silicon On Insulator ◽

Wafer Level ◽

3D Integration ◽

Edge Chipping ◽

3D Ics ◽

Process Compatibility ◽

Wafer Thinning ◽

Thinning Process

AbstractMonolithic wafer-level three-dimensional (3D) ICs based upon bonding of processed wafers and die-to-wafer 3D ICs based upon bonding die to a host wafer require additional planarization considerations compared to conventional planar ICs and wafer-scale packaging. Various planarization issues are described, focusing on the more stringent technology requirements of monolithic wafer-level 3D ICs. The specific 3D IC technology approach considered here consists of wafer bonding with dielectric adhesives, a three-step thinning process of grinding, polishing and etching, and an inter-wafer interconnect process using copper damascene patterning. The use of a bonding adhesive to relax pre-bonding wafer planarization requirements is a key to process compatibility with standard IC processes. Minimizing edge chipping during wafer thinning requires understanding of the relationships between wafer bonding, thinning and pre-bonding IC processes. The advantage of silicon-on-insulator technology in alleviating planarization issues with wafer thinning for 3D ICs is described.

Download Full-text

Three-Dimensional Integration Technology for Advanced Focal Planes

MRS Proceedings ◽

10.1557/proc-1112-e01-02 ◽

2008 ◽

Vol 1112 ◽

Cited By ~ 2

Author(s):

Craig Lewis Keast ◽

Brian Aull ◽

James Burns ◽

Chenson Chen ◽

Jeff Knecht ◽

...

Keyword(s):

Focal Plane ◽

Three Dimensional ◽

Focal Plane Arrays ◽

Silicon On Insulator ◽

Wafer Level ◽

Integration Technology ◽

Electrical Interconnection ◽

Circuit Integration ◽

Micrometer Scale ◽

Soi Technology

AbstractWe have developed a three-dimensional (3D) circuit integration technology that exploits the advantages of silicon-on-insulator (SOI) technology to enable wafer-level stacking and micrometer-scale electrical interconnection of fully fabricated circuit wafers. This paper describes the 3D technology and discusses some of the advanced focal plane arrays that have been built using it.

Download Full-text