Mechanisms of Low-Temperature Ti/Si-Based Wafer Bonding

2005 ◽  
Vol 863 ◽  
Author(s):  
Jian Yu ◽  
Yinmin Wang ◽  
Arthur W. Haberl ◽  
Hassa Bakhru ◽  
Jian-Qiang Lu ◽  
...  
Keyword(s):  
Silicon Wafer ◽  
Wafer Bonding ◽  
Rutherford Backscattering Spectrometry ◽  
Three Dimensional ◽  
Amorphous Layer ◽  
Bonding Interface ◽  
Native Oxide ◽  
Wafer Level ◽  
Transmission Electron ◽  
Strong Adhesion

AbstractThree-dimensional (3D) wafer-level integration is receiving increased attention with various wafer bonding approaches being evaluated. Recently, we explored an alternative lowtemperature Ti/Si-based wafer bonding, in which an oxidized silicon wafer was successfully bonded with a prime silicon wafer at 400°C using 30 nm sputtered Ti as adhesive. The bonded pairs show excellent bonding uniformity and mechanical integrity. Rutherford backscattering spectrometry (RBS) was applied to confirm the interdiffusion occurred in the interlayer. The bonding interface was examined by high-resolution transmission electron microscopy (HRTEM) assisted with electron energy loss spectroscopy (EELS) elemental mapping and energy dispersive X-ray spectroscopy (EDX). Characterization of the bonding interface indicates the strong adhesion achieved is attributed to an amorphous layer formed by interdiffusion of Si and oxygen into Ti interlayer and the unique ability to reduce native oxide (SiO2) by Ti even at low temperatures.

200. mm Silicon Wafer-to-Wafer Bonding with Thin Ti Layer under BEOL-Compatible Process Conditions

2004 ◽  
Vol 843 ◽  
Author(s):  
J. Yu ◽  
J. J. McMahon ◽  
J.-Q. Lu ◽  
R. J. Gutmann
Keyword(s):  
Wafer Bonding ◽  
Three Dimensional ◽  
Complete Removal ◽  
External Pressure ◽  
Reduced Form ◽  
Process Conditions ◽  
Manufacturing Cost ◽  
Wafer Level ◽  
Integrity Test ◽  
Wafer Pair

ABSTRACTWafer level monolithic three-dimensional (3D) integration is an emerging technology to realize enhanced performance and functionality with reduced form-factor and manufacturing cost. The cornerstone for this 3D processing technology is full-wafer bonding under back-end-of-the-line (BEOL) compatible process conditions. For the first time to our knowledge, we demonstrate nearly void-free 200 mm wafer-to-wafer bonding with an ultra-thin Ti adhesive coating, annealed at BEOL-compatible temperature (400 °C) in vacuum with external pressure applied. Mechanical integrity test showed that bonded wafer pair survived after a stringent three-step thinning process (grinding/polishing/wet-etching) with complete removal of top Si wafer, while allowing optical inspection of bonding interface. Mechanisms contributing to the strong bonding at Ti/Si interface are briefly discussed.

Wafer Bonding of Diamond Films to Silicon for Silicon-on-Insulator Technology

2001 ◽  
Vol 686 ◽  
Author(s):  
Gleb N. Yushin ◽  
Scott D. Wolter ◽  
Alexander V. Kvit ◽  
Ramon Collazo ◽  
John T. Prater ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
Diamond Films ◽  
Polycrystalline Diamond ◽  
Amorphous Layer ◽  
Silicon On Insulator ◽  
Acoustic Microscopy ◽  
Cross Sectional ◽  
Silicon Carbon ◽  
Transmission Electron ◽  
Silicon On Insulator Technology

AbstractPolycrystalline diamond films previously grown on silicon were polished to an RMS roughness of 15 nm and bonded to the silicon in a dedicated ultrahigh vacuum bonding chamber. Successful bonding under a uniaxial mechanical stress of 32 MPa was observed at temperatures as low as 950°C. Scanning acoustic microscopy indicated complete bonding at fusion temperatures above 1150°C. Cross-sectional transmission electron microscopy later revealed a 30 nm thick intermediate amorphous layer consisting of silicon, carbon and oxygen.

Nanothick Layer Transfer of Hydrogen-implanted Wafer Using Polysilicon Sacrificial Layer

2006 ◽  
Vol 921 ◽  
Author(s):  
C. H. Huang ◽  
C. L. Chang ◽  
Y. Y. Yang ◽  
T. Suryasindhu ◽  
W. -C. Liao ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Silicon Wafer ◽  
Wafer Bonding ◽  
Sacrificial Layer ◽  
Silicon Layer ◽  
Bonding Layer ◽  
Transmission Electron ◽  
Nanostructure Material ◽  
Polysilicon Layer ◽  
Material Fabrication

AbstractAn ion implantation-wafer bonding-layer splitting based 2-D nanostructure material fabrication method using polysilicon sacrificial layer for forming nanothick SOI materials without using post-thinning processes is presented in this paper. Polysilicon layer was initially deposited on the thermal oxidized surface of silicon wafer prior to the ion implantation step to achieve the hydrogen-rich buried layer which depth from the top surface is less than 100 nm in the as-implanted silicon wafer. Before this as-implanted wafer being bonded with a handle wafer, the polysilicon layer was removed by a wet etching method. A nanothick silicon layer was then successfully transferred onto a handle wafer after wafer bonding and layer splitting steps. The thickness of the final transferred silicon layer was 100 nm measured by transmission electron microscopy (TEM).

Ion-Beam-Induced Silicide Formation in Nickel Thin Films on Silicon

1982 ◽  
Vol 18 ◽  
Author(s):  
L. J. Chen ◽  
C. Y. Hou
Keyword(s):  
Thin Films ◽  
Driving Force ◽  
Rutherford Backscattering Spectrometry ◽  
Ion Beam ◽  
Amorphous Layer ◽  
Critical Value ◽  
Silicide Formation ◽  
Nickel Thin Films ◽  
Transmission Electron ◽  
Post Implantation

As+-ion-induced silicide formation in nickel thin films on silicon was investigated by Rutherford backscattering spectrometry and transmission electron microscopy. The emphasis was on the study of ion-beam-induced microstructural changes.For 160 keV As+ implantation, amorphization of the interface occurred at a dose of 5 × 1014 cm−2. Ni2Si was found together with an amorphous layer after a 1 × 1015 cm−2 bombardment. For Ni/Si(100) the surface layer became completely amorphous after implantation to 5×1015 cm−2. Silicides were found after a 1×1016 cm−2 irradiation. The amorphous layer was not stable enough to withstand the enormous chemical driving force causing the formation of crystalline silicides as the composition ratio Nsi/NNi reached a critical value. A similar trend for ion-beam-induced reactions was found for 190 keV As+ implantation on Ni/Si(111) as for 160 keV implantation.The results of post-implantation annealing showed major differences from those obtained for directly annealed samples.

Ni, Pd, and Pt on GaAs: A comparative study of interfacial structures, compositions, and reacted film morphologies

1987 ◽  
Vol 2 (2) ◽  
pp. 262-275 ◽  
Author(s):  
T. Sands ◽  
V. G. Keramidas ◽  
A. J. Yu ◽  
K-M. Yu ◽  
R. Gronsky ◽  
...  
Keyword(s):  
Thin Film ◽  
Noble Metals ◽  
Rutherford Backscattering Spectrometry ◽  
Native Oxide ◽  
Nominal Composition ◽  
X Rays ◽  
Energy Dispersive Analysis ◽  
Isothermal Sections ◽  
Transmission Electron ◽  
Interfacial Structures

The reactions between (100) GaAs and the near-noble metals Ni, Pd, and Pt have been investigated by application of high-resolution transmission electron microscopy (TEM), energy-dispersive analysis of x-rays in the scanning TEM and Rutherford backscattering spectrometry. Emphasis is placed on the evolution of the phase distributions, film compositions, and interface morphologies during annealing at temperatures up to 480°C. The first phase in the Ni/GaAs reaction is shown to have the nominal composition Ni3GaAs. Ternary phases of the type PdxGaAs are also found to be the dominant products of the Pd/GaAs reaction. Conversely, only binary phases result from the Pt/GaAs reaction. These observations are used to construct isothermal sections of the M-Ga-As thin-film phase diagrams. The behavior of a thin (1–2 nm) native oxide-hydrocarbon layer during the Ni/GaAs, Pd/GaAs, and Pt/GaAs reactions is also investigated. Only the Ni/GaAs reaction is noticeably impeded in some regions by this intervening layer. In contrast, the Pd/GaAs and Pt/GaAs reactions tend to mechanically disperse the native oxide layers.

A Novel Process to Form Epitaxial Si Structures With Buried Silicide

1991 ◽  
Vol 235 ◽  
Author(s):  
YU. N. Erokhin ◽  
R. Grotzschel ◽  
S. R. Oktyabrski ◽  
S. Roorda ◽  
W. Sinke ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Thermal Annealing ◽  
Crystalline Silicon ◽  
Rutherford Backscattering Spectrometry ◽  
Amorphous Layer ◽  
Cross Sectional ◽  
X Ray ◽  
Metal Atoms ◽  
Transmission Electron ◽  
High Metal

ABSTRACTThe interaction during low temperature thermal annealing of metal atoms from a Ni film evaporated on top of Si structures with a buried amorphous layer formed by ion implantation has been investigated. Rutherford Backscattering Spectrometry (RBS)/channeling, cross-sectional transmission electron microscopy (XTEM) and X-ray microanalysis were used to determine structures and compositions. It is shown that the combination of such silicon properties as the increased rate of silicidation reaction for amorphous silicon with respect to the crystalline one in combination with high metal atom diffusivity leads to formation of buried epitaxial Ni silicide islands at the interface between the amorphous and the top crystalline silicon layers. During thermal annealing at temperatures as low as 350° C, these islands move through the a-Si layer leaving behind epitaxially recrystallized Si.

Planarization Issues in Wafer-Level Three-Dimensional (3D) Integration

2004 ◽  
Vol 816 ◽  
Author(s):  
J.-Q. Lu ◽  
G. Rajagopalan ◽  
M. Gupta ◽  
T.S. Cale ◽  
R.J. Gutmann
Keyword(s):  
Wafer Bonding ◽  
Three Dimensional ◽  
Silicon On Insulator ◽  
Wafer Level ◽  
3D Integration ◽  
Edge Chipping ◽  
3D Ics ◽  
Process Compatibility ◽  
Wafer Thinning ◽  
Thinning Process

AbstractMonolithic wafer-level three-dimensional (3D) ICs based upon bonding of processed wafers and die-to-wafer 3D ICs based upon bonding die to a host wafer require additional planarization considerations compared to conventional planar ICs and wafer-scale packaging. Various planarization issues are described, focusing on the more stringent technology requirements of monolithic wafer-level 3D ICs. The specific 3D IC technology approach considered here consists of wafer bonding with dielectric adhesives, a three-step thinning process of grinding, polishing and etching, and an inter-wafer interconnect process using copper damascene patterning. The use of a bonding adhesive to relax pre-bonding wafer planarization requirements is a key to process compatibility with standard IC processes. Minimizing edge chipping during wafer thinning requires understanding of the relationships between wafer bonding, thinning and pre-bonding IC processes. The advantage of silicon-on-insulator technology in alleviating planarization issues with wafer thinning for 3D ICs is described.

Initiation and Evolution of Epitaxial Growth of GaAs on CaF2/Si (111) Substrates

1993 ◽  
Vol 317 ◽  
Author(s):  
Weidan Li ◽  
Takayoshi Anan ◽  
Thomas Thundat ◽  
Leo J. Schowalter
Keyword(s):  
Electron Microscopy ◽  
Rutherford Backscattering Spectrometry ◽  
Three Dimensional ◽  
Optimal Growth ◽  
Two Dimensional ◽  
Subsequent Growth ◽  
Mbe Growth ◽  
Force Microscopy ◽  
Atomic Force ◽  
Transmission Electron

AbstractIn this work, MBE growth of GaAs on CaF2/Si (111) substrates has been studied with both Rutherford backscattering spectrometry, transmission electron microscopy and atomic force Microscopy. It has been observed that, under certain conditions, a chemical reaction between As adatoms and the CaF2 layers can be induced, by which a more stable As layer on the CaF2 surface is formed. The existence of the As layer modifies the CaF2 surface free energy, which, if properly controlled, leads to two-dimensional (2D) nucleation of GaAs on the CaF2/Si (111) surface as opposed to the more commonly observed three-dimensional (3D) growth. Artificial Modification of the CaF2 (111) surface by introducing Ca prior to GaAs growth is also discussed as a promising way to achieve 2D nucleation. In subsequent growth, two kinds of twins have been observed. All samples were observed to have Micro-twins near the GaAs/CaF2 interface. These twins can be suppressed during the first 1000Å, if the layer is grown in a narrow optimal growth window. Otherwise, the growth will be in a 3D Mode at lower temperatures, or it will suffer from the formation of large rotational twins at higher temperatures. It has been observed that growth on vicinal substrates tilted toward [112] azimuth is helpful in suppressing the development of rotational twins so that growth on these substrates have a wider optimal growth window. Surface Morphology of CaF2 epitaxial layers grown on Si (111) substrates with different vicinal angles has also been investigated. It May have significant impact on the twin development during subsequent GaAs growth.

scholarly journals Transmission Electron Microscopy Studies of Electrical Active GaAs/GaN Interface Obtained by Wafer Bonding

2002 ◽  
Vol 722 ◽  
Author(s):  
J. Jasinski ◽  
Z. Liliental-Weber ◽  
S. Estrada ◽  
E. Hu
Keyword(s):  
Electron Microscopy ◽  
Transmission Electron Microscopy ◽  
Wafer Bonding ◽  
Native Oxide ◽  
Interface Area ◽  
Plan View ◽  
Thermal Expansion Coefficients ◽  
Transmission Electron ◽  
Direct Wafer Bonding ◽  
Expansion Coefficients

AbstractTransmission electron microscopy (TEM) and energy dispersive X-ray spectroscopy (EDX) studies of GaAs/GaN interfaces, obtained by direct wafer bonding, are presented. TEM observations show that most of the interface area was well bonded. A thin oxide layer, confirmed by EDX, was present at the interface in the well-bonded regions. Plan-view TEM studies showed the presence of two dislocation networks in such regions. They formed to accommodate: (1) tilt between bonded crystals and (2) strain, which appeared during sample cooling due to mismatch in thermal expansion coefficients. Asymmetrical, often elongated, cavities, formed on the GaAs side, were present at the interface between the well-bonded regions. It was shown by EDX that the walls of these cavities are covered with native oxide.

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