scholarly journals Integrating Side Channel Security in the FPGA Hardware Design Flow

2021 ◽  
pp. 275-290
Author(s):  
Alessandro Barenghi ◽  
Matteo Brevi ◽  
William Fornaciari ◽  
Gerardo Pelosi ◽  
Davide Zoni
Keyword(s):  
Hardware Design ◽  
Design Flow ◽  
Side Channel

scholarly journals Towards Efficient and Automated Side Channel Evaluations at Design Time

10.29007/mbf3 ◽  
2018 ◽  
Author(s):  
Danilo Šijačić ◽  
Josep Balasch ◽  
Bohan Yang ◽  
Santosh Ghosh ◽  
Ingrid Verbauwhede
Keyword(s):  
Experimental Validation ◽  
State Of The Art ◽  
Information Leakage ◽  
Design Flow ◽  
Side Channel ◽  
Cell Design ◽  
Standard Cell ◽  
Side Channel Analysis ◽  
Design Time ◽  
Channel Analysis

Models and tools developed by the semiconductor community have matured over decades of use. As a result, hardware simulations can yield highly accurate and easily automated pre-silicon estimates for e.g. timing and area figures. In this work we design, implement, and evaluate CASCADE, a framework that combines a largely automated full-stack standard-cell design flow with the state of the art techniques for side channel analysis. We show how it can be used to efficiently evaluate side channel leakage prior to chip manufacturing. Moreover, it is independent of the underlying countermeasure and it can be applied starting from the earliest stages of the design flow. Additionally, we provide experimental validation through assessment of the side channel security of representative cryptographic circuits. We discuss aspects related to the performance, scalability, and utility to the designers. In particular, we show that CASCADE can evaluate information leakage with 1 million simulated traces in less than 4 hours using a single desktop workstation, for a design larger than 100kGE.

Dynamic Reconfiguration for Internal Monitoring Services

2016 ◽  
pp. 124-136
Author(s):  
Julio Daniel Dondo Gazzano ◽  
Fernando Rincon Calle ◽  
Julian Caba ◽  
David de la Fuente ◽  
Jesus Barba Romero
Keyword(s):  
Quality Assurance ◽  
Monitoring System ◽  
Hardware Design ◽  
Dynamic Reconfiguration ◽  
Design Flow ◽  
Added Value ◽  
Partial Reconfiguration ◽  
Dynamically Reconfigurable ◽  
Simulation Process ◽  
Hardware Component

In hardware design flow, testing is the most important step to hardware quality assurance before a hardware component is released. However simulation and verification during design steps are not enough to guarantee a system without failures. In many cases the system fails after have been deployed. Dynamically reconfigurable FPGAs have the ability to reconfigure part of its architecture during run time without stopping the whole system. This feature is an added value that can be exploited for internal system monitoring and verification. Using partial reconfiguration, an Internal Monitoring System can be implemented in reconfigurable areas for monitoring different conditions and signals in the circuit, after implementation. This allows detecting and identifying those failures that were not possible to detect during simulation process.

scholarly journals AHEAD: Automatic Holistic Energy-Aware Design Methodology for MLP Neural Network Hardware Generation in Proactive BMI Edge Devices

Energies ◽  
2020 ◽  
Vol 13 (9) ◽  
pp. 2180
Author(s):  
Nan-Sheng Huang ◽  
Yi-Chung Chen ◽  
Jørgen Christian Larsen ◽  
Poramate Manoonpong
Keyword(s):  
Neural Network ◽  
Low Power ◽  
Design Methodology ◽  
Hardware Design ◽  
Design Flow ◽  
Floating Point ◽  
Energy Aware ◽  
Mlp Neural Network ◽  
Neural Recordings ◽  
Neural Network Hardware

The prediction of a high-level cognitive function based on a proactive brain–machine interface (BMI) control edge device is an emerging technology for improving the quality of life for disabled people. However, maintaining the stability of multiunit neural recordings is made difficult by the nonstationary nature of neurons and can affect the overall performance of proactive BMI control. Thus, it requires regular recalibration to retrain a neural network decoder for proactive control. However, retraining may lead to changes in the network parameters, such as the network topology. In terms of the hardware implementation of the neural decoder for real-time and low-power processing, it takes time to modify or redesign the hardware accelerator. Consequently, handling the engineering change of the low-power hardware design requires substantial human resources and time. To address this design challenge, this work proposes AHEAD: an automatic holistic energy-aware design methodology for multilayer perceptron (MLP) neural network hardware generation in proactive BMI edge devices. By taking a holistic analysis of the proactive BMI design flow, the approach makes judicious use of the intelligent bit-width identification (BWID) and configurable hardware generation, which autonomously integrate to generate the low-power hardware decoder. The proposed AHEAD methodology begins with the trained MLP parameters and golden datasets and produces an efficient hardware design in terms of performance, power, and area (PPA) with the least loss of accuracy. The results show that the proposed methodology is up to a 4X faster in performance, 3X lower in terms of power consumption, and achieves a 5X reduction in area resources, with exact accuracy, compared to floating-point and half-floating-point design on a field-programmable gate array (FPGA), which makes it a promising design methodology for proactive BMI edge devices.

Dielectrophoresis Separation of Colon Cancer Cell

2009 ◽  
Author(s):  
Fang Yang ◽  
Xiaoming Yang ◽  
H. Jiang ◽  
P. Wood ◽  
W. Hrushesky ◽  
...  
Keyword(s):  
Cancer Cell ◽  
Cancer Diagnosis ◽  
Collection Efficiency ◽  
Hct116 Cell ◽  
Main Channel ◽  
Colon Cancer Cell ◽  
Design Flow ◽  
Side Channel ◽  
Chip Design ◽  
Electric Activation

Separation of cancer cells from the other biological cells is important for clinical cancer diagnosis and cancer treatment. In this presentation, we use conventional dielectrophoresis (c-DEP) in a microfluidic chip to manipulate and collect colorectal cancer HCT116 cell. It is noticed that at particular AC frequency band, the HCT116 cell are deflected to a side channel from a main channel clearly after the electric activation. This motion caused by negative DEP can be used to separate the cancer cell from others. In this manuscript, we report the chip design, flow condition, the DEP spectrum of the cancer cell, and the separation and collection efficiency as well.

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