Evolution of Wafer Bonding Technology and Applications from Wafer-Level Packaging to Micro/Nanofluidics-Enhanced Sensing

2021 ◽  
pp. 187-215
Author(s):  
Jikai Xu ◽  
Zhihao Ren ◽  
Bowei Dong ◽  
Chenxi Wang ◽  
Yanhong Tian ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Bonding Technology

High Precision Low Temperature Direct Wafer Bonding Technology for Wafer-Level 3D ICs Manufacturing

2016 ◽  
Vol 75 (9) ◽  
pp. 345-353 ◽  
Author(s):  
F. Kurz ◽  
T. Plach ◽  
J. Suss ◽  
T. Wagenleitner ◽  
D. Zinner ◽  
...  
Keyword(s):  
Low Temperature ◽  
High Precision ◽  
Wafer Bonding ◽  
Wafer Level ◽  
3D Ics ◽  
Direct Wafer Bonding ◽  
Bonding Technology

Metal Wafer Bonding for MEMS Applications

2008 ◽  
Vol 1139 ◽  
Author(s):  
Viorel Dragoi ◽  
Gerald Mittendorfer ◽  
Franz Murauer ◽  
Erkan Cakmak ◽  
Eric Pabo
Keyword(s):  
Intermetallic Compound ◽  
Eutectic Alloy ◽  
Wafer Bonding ◽  
Alloy Layer ◽  
Manufacturing Processes ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Metal Diffusion ◽  
Metal Layers ◽  
Different Levels

AbstractMetal layers can be used as bonding layers at wafer-level in MEMS manufacturing processes for device assembly as well as just for electrical integration of different levels. One has to distinguish between two main types of processes: metal diffusion bonding and bonding with formation of an interface eutectic alloy layer or an intermetallic compound. The different process principles determine also the applications area for each. From electrical interconnections to wafer-level packaging (with emphasis on vacuum packaging) metal wafer bonding is a very important technology in MEMS manufacturing processes.

SiP(System in Package) Solutions with Wafer Level Packaging Technology

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002226-002253 ◽  
Author(s):  
In Soo Kang ◽  
Jong Heon (Jay) Kim
Keyword(s):  
Embedded System ◽  
High Performance ◽  
Low Cost ◽  
Wafer Level ◽  
Molding Compound ◽  
Wafer Level Packaging ◽  
Ic Packaging ◽  
Chip Size ◽  
Bonding Technology ◽  
Small Form Factor

In mobile application, the WLP technology has been developing to make whole package size almost same as chip size. However, the I/O per chip unit area has increased so that it gets difficult to realize ideal pad pitch for better reliability. Recently, to achieve the thin and small size, high performance and low cost semiconductor package, Embedding Die and Fanout Technologies have been suggested and developed based on wafer level processing. In this work, as a solution of system in package, wafer level embedded package and fanout technology will be reviewed. Firstly, Wafer level embedded System in Package (WL-eSiP) which has daughter chip (small chip) embedded inside mother chip (bigger chip) without any special substrate has been suggested and developed. To realize wafer level embedded system in package (WL-eSiP), wafer level based new processes like wafer level molding for underfilling and encapsulation by molding compound without any special substrate have been applied and developed, including high aspect ratio Cu bumping, mold thinning and chip-to-wafer flipchip bonding. Secondly, Fan-out Package is considered as alternative package structure which means merged package structure of WLCSP (wafer level chip size package) and PCB process. We can make IC packaging widen area for SIP(System in Package) or 3D package. In addition, TSV and IPD are key enabling technology to meet market demands because TSV interconnection can provide wider bandwidth and high transmission speed due to vertical one compared to wire bonding technology and IPD can provide higher performance, more area saving to be assembled and small form factor compared to discrete passive components.

Patterned Permanent Bonding of Benzocyclobutene Based Dielectric Materials for Advanced Wafer Level Packaging

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 000886-000912
Author(s):  
Jong-Uk Kim ◽  
Anupam Choubey ◽  
Rosemary Bell ◽  
Hua Dong ◽  
Michael Gallagher ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
Dielectric Materials ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Integration Schemes ◽  
Device Reliability ◽  
Package Size ◽  
Microelectronics Industry ◽  
Improve Device ◽  
Joining Process

The microelectronics industry is being continually challenged to decrease package size, lower power consumption and improve device performance for the mobile communication and server markets. In order to keep pace with these requirements, device manufacturers and assembly companies are focused on developing 3D-TSV integration schemes that will require stacking of 50 um thinned wafers with gaps of 15 microns or less. While conventional underfill approaches have been demonstrated for chip to chip and chip to wafer schemes, new materials and processes are required for wafer to wafer bonding given the target bondline and wafer handling issues. Photopatternable, low temperature curable dielectrics offer a potential solution to solve the issues by eliminating the need for flow and material entrapment during the joining process. This should result in a simplified bonding process that enables wafer to wafer bonding with improved device reliability. In this work, we will focus on validating the critical steps including patterning and bonding that are required to demonstrate the utility of this process using an aqueous developable benzocyclobutene based photodielectric material.

Wafer Bonding Processes for the Manufacture of Microsystems

2008 ◽  
Author(s):  
Tony Rogers ◽  
Nick Aitken
Keyword(s):  
Bond Strength ◽  
Wafer Bonding ◽  
High Efficiency ◽  
Glass Frit ◽  
Acoustic Microscopy ◽  
Anodic Bonding ◽  
High Yield ◽  
Mems Devices ◽  
Wafer Level ◽  
Wafer Level Packaging

Wafer bonding is a widely used step in the manufacture of Microsystems, and serves several purposes: • Structural component of the MEMS device. • First level packaging. • Encapsulation of vacuum or controlled gas. In addition the technology is becoming more widely used in IC fabrication for wafer level packaging (WLP) and 3D integration. It is also widely used for the fabrication of micro fluidic structures and in the manufacture of high efficiency LED’s. Depending on the application, temperature constraints, material compatibility etc. different wafer bonding processes are available, each with their own benefits and drawbacks. This paper describes various wafer bonding processes that are applicable, not only to silicon, but other materials such as glass and quartz that are commonly used in MEMS devices. The process of selecting the most appropriate bonding process for the particular application is presented along with examples of anodic, glass frit, eutectic, direct, adhesive and thermo-compression bonding. The examples include appropriate metrology for bond strength and quality. The paper also addresses the benefits of being able to treat the wafer surfaces in-situ prior to bonding in order to improve yield and bond strength, and also discusses equipment requirements for achieving high yield wafer bonding, along with high precision alignment accuracy, good force and temperature uniformity, high wafer throughput, etc. Some common problems that can affect yield are identified and discussed. These include local temperature variations, that can occur with anodic bonding, and how to eliminate them; how to cope with materials of different thermal expansion coefficient; how best to deal with out-gassing and achieve vacuum encapsulation; and procedures for multi-stacking wafers of differing thicknesses. The presentation includes infra-red and scanning acoustic microscopy images of various bond types, plus some examples of what can go wrong if the correct manufacturing protocol is not maintained.

Hermetic Packaging Technique Featuring Through-Wafer Interconnects and Low Temperature Direct Bond

2008 ◽  
Author(s):  
James Lee ◽  
Tony Rogers
Keyword(s):  
Low Temperature ◽  
Wafer Bonding ◽  
High Strength ◽  
Mems Devices ◽  
Wafer Level ◽  
Direct Bond ◽  
Hermetic Packaging ◽  
Wafer Level Packaging ◽  
Hermetic Seal ◽  
Silicon Silicon

A novel wafer level packaging method suitable for low production volumes, R&D, and multi-project wafers is presented, providing a hermetic seal suitable for vacuum encapsulation with wafers bonded at a low temperature. Hermetic through-wafer interconnects are bump bonded to a CMOS chip encapsulated by bonding a cap wafer after activating surfaces with free radicals, the Silicon-Silicon direct bond is then annealed to a high strength at 200°C to avoid chip damage. The application for which this system is proposed is an implantable multi-contact active nerve electrode for the treatment of epilepsy via vagus nerve stimulation. Although intended for human implantation of integrated systems, this technology may be applied across a range of devices requiring hermetic or vacuum sealing and through-wafer interconnection. Solid electroplated through-wafer interconnects (aspect ratio 5) enable hermetic interconnection of direct bonded packages with low connection impedance, offering benefits across a range of packaging applications. A key feature of this packaging method is it’s versatility, the proposed embodiment features chip to wafer bonding with an ASIC, but the package is equally suitable for MEMS devices and also for wafer to wafer bonding.

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