scholarly journals CVR: A Continuously Variable Rate LDPC Decoder Using Parity Check Extension for Minimum Latency

2020 ◽  
Author(s):  
Sina Pourjabar ◽  
Gwan S. Choi
Keyword(s):  
Variable Rate ◽  
Parity Check ◽  
Ldpc Decoder ◽  
Minimum Latency

scholarly journals A novel error correction protocol for continuous variable quantum key distribution

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Kadir Gümüş ◽  
Tobias A. Eriksson ◽  
Masahiro Takeoka ◽  
Mikio Fujiwara ◽  
Masahide Sasaki ◽  
...  
Keyword(s):  
Error Correction ◽  
Quantum Key Distribution ◽  
Ldpc Codes ◽  
Key Distribution ◽  
Continuous Variable ◽  
Early Termination ◽  
Parity Check ◽  
Secret Key ◽  
Ldpc Decoder ◽  
And Performance

AbstractReconciliation is a key element of continuous-variable quantum key distribution (CV-QKD) protocols, affecting both the complexity and performance of the entire system. During the reconciliation protocol, error correction is typically performed using low-density parity-check (LDPC) codes with a single decoding attempt. In this paper, we propose a modification to a conventional reconciliation protocol used in four-state protocol CV-QKD systems called the multiple decoding attempts (MDA) protocol. MDA uses multiple decoding attempts with LDPC codes, each attempt having fewer decoding iteration than the conventional protocol. Between each decoding attempt we propose to reveal information bits, which effectively lowers the code rate. MDA is shown to outperform the conventional protocol in regards to the secret key rate (SKR). A 10% decrease in frame error rate and an 8.5% increase in SKR are reported in this paper. A simple early termination for the LDPC decoder is also proposed and implemented. With early termination, MDA has decoding complexity similar to the conventional protocol while having an improved SKR.

scholarly journals Hardwarearchitektur für einen universellen LDPC Decoder

2009 ◽  
Vol 7 ◽  
pp. 213-218
Author(s):  
C. Beuschel ◽  
H.-J. Pfleiderer
Keyword(s):  
Ldpc Code ◽  
Low Density ◽  
Parity Check ◽  
Wird Eine ◽  
Ldpc Decoder ◽  
Low Density Parity Check

Abstract. Im vorliegenden Beitrag wird eine universelle Decoderarchitektur für einen Low-Density Parity-Check (LDPC) Code Decoder vorgestellt. Anders als bei den in der Literatur häufig beschriebenen Architekturen für strukturierte Codes ist die hier vorgestellte Architektur frei programmierbar, so dass jeder beliebige LDPC Code durch eine Änderung der Initialisierung des Speichers für die Prüfmatrix mit derselben Hardware decodiert werden kann. Die größte Herausforderung beim Entwurf von teilparallelen LDPC Decoder Architekturen liegt im konfliktfreien Datenaustausch zwischen mehreren parallelen Speichern und Berechnungseinheiten, wozu ein Mapping und Scheduling Algorithmus benötigt wird. Der hier vorgestellte Algorithmus stützt sich auf Graphentheorie und findet für jeden beliebigen LDPC Code eine für die Architektur optimale Lösung. Damit sind keine Wartezyklen notwendig und die Parallelität der Architektur wird zu jedem Zeitpunkt voll ausgenutzt.

An Efficient VLSI Architecture for Nonbinary LDPC Decoder with Adaptive Message Control

2015 ◽  
Vol 4 (1) ◽  
pp. 6
Author(s):  
Varatharajan Ramachandran
Keyword(s):  
Power Consumption ◽  
Vlsi Architecture ◽  
Ldpc Codes ◽  
Parity Check ◽  
Decoding Complexity ◽  
Ldpc Decoder ◽  
Message Length ◽  
Low Density Parity Check ◽  
Decoder Architecture ◽  
Memory Accesses

<p>A new decoder architecture for nonbinary low-density parity check (LDPC) codes is presented in this paper to reduce the hardware operational complexity and power consumption. Adaptive message control (AMC) is to achieve the low decoding complexity,  that dynamically trims the message length of belief information to reduce the amount of memory accesses and arithmetic operations. A new horizontal nonbinary LDPC decoder architecture is developed to implement AMC. Key components in the architecture have been designed with the consideration of variable message lengths to leverage the benefit of the proposed AMC. Simulation results demonstrate that the proposed nonbinary LDPC decoder architecture can significantly reduce hardware operations and power consumption as compared with existing work with negligible performance degradation.</p>

scholarly journals On the Design of Punctured Low Density Parity Check Codes for Variable Rate Systems

2017 ◽  
Vol 1 (2) ◽  
pp. 88 ◽  
Author(s):  
Marco Baldi ◽  
Franco Chiaraluce
Keyword(s):  
Ldpc Codes ◽  
The Other ◽  
Variable Rate ◽  
Parity Check ◽  
Pragmatic Approach ◽  
Parity Check Matrix ◽  
Tanner Graph ◽  
Low Density Parity Check ◽  
Check Matrix ◽  
Parity Check Codes

The authors face the problem of designing good LDPC codes for applications requiring variable, that is adaptive, rates. More precisely, the object of the paper is twofold. On one hand, we propose a deterministic (not random) procedureto construct good LDPC codes without constraints on the code dimension and rate. The method is based on the analysis and optimization of the local cycles length in the Tanner graph and gives the designer the chance to control complexity of the designed codes. On the other hand, we present a novel puncturing strategy which acts directly on the parity check matrix of the code, starting from the lowest rate needed, in order to allow the design of higher rate codes avoiding additional complexity of the co/decoding hardware. The efficiency of the proposed solution is tested through a number of numerical simulations. In particular, the puncturing strategy is applied for designing codes with rate variable between 0.715 and 0.906. The designed codes are used in conjunction with M-QAM constellations through a pragmatic approach that, however, yields very promising results.

scholarly journals LDPC Decoder of High Speed Multi-Rate DVB-S2 Based on FPGA

2019 ◽  
Vol 37 (2) ◽  
pp. 299-307 ◽  
Author(s):  
TianJiao Xie ◽  
Bo Li ◽  
Mao Yang ◽  
Zhongjiang Yan
Keyword(s):  
High Speed ◽  
State Of The Art ◽  
Ldpc Codes ◽  
The State ◽  
Elementary Transformation ◽  
Parity Check ◽  
Ldpc Decoder ◽  
Art Works ◽  
Decoder Architecture ◽  
Lower Triangular

A multi-rate LDPC decoder architecture for DVB-S2 codes based on FPGA is proposed. Through elementary transformation on the parity check matrices of DVB-S2 LDPC codes, a new matrix whose left is a QC sub-matrix and right is Transformation of Staircase lower triangular (TST) sub-matrix is obtained. The QC and TST are designed separately, therefore the successful experience of the most popular Quasi-Cyclic (QC) LDPC decoder architecture can be drawn on. While for TST sub-matrix, the variable nodes updating only need to be considered and the check nodes updating is realized compatibility with QC sub-matrix. Based on the proposed architectures, a multi-rate LDPC decoder implemented on Xilinx XC7VX485T FPGA can achieve the maximum decoding throughput of 2.5 Gbit/s at the 20 iterations when the operating frequency is 250 MHz, which demonstrates the highest throughput compared with the state-of-the-art works.

scholarly journals Conception of a new LDPC decoder with hardware implementation on FPGA card

2014 ◽  
Vol 3 (4) ◽  
pp. 451
Author(s):  
Anas El habti El idrissi ◽  
Rachid El Gouri ◽  
Hlou Laamari
Keyword(s):  
Error Detection ◽  
Matrix Equation ◽  
Coding Theory ◽  
Ldpc Codes ◽  
Low Density ◽  
Parity Check ◽  
Fast Encoding ◽  
Ldpc Decoder ◽  
Low Density Parity Check ◽  
Simplified Algorithm

Low Density Parity-Check codes are one of the hottest topics in coding theory nowadays. Equipped with very fast encoding and decoding algorithms, LDPC codes are very attractive both theoretically and practically. In this paper, A simplified algorithm for decoding Low-Density Parity-Check (LDPC) codes is proposed with a view to reduce the implementation complexity, this algorithm is based on a simple matrix equation which must be resolved in order to calculate all possible solutions of this equation, and then a simple circuit will be used to determine the errors produced during the transmission channel. First, we developed the design of the proposed algorithm second, we generated and simulated the hardware description language source code using Quartus software tools and finally we implemented the new algorithm of LDPC codes on FPGA card. Keywords: Bit-Flipping Algorithm, Error Detection, FPGA Card, LDPC Decoder, Matrix Equation.

scholarly journals LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization

VLSI Design ◽  
2013 ◽  
Vol 2013 ◽  
pp. 1-14 ◽  
Author(s):  
Tinoosh Mohsenin ◽  
Houshmand Shirani-mehr ◽  
Bevan M. Baas
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
State Of The Art ◽  
Average Power ◽  
Parity Check ◽  
Ldpc Decoder ◽  
Low Density Parity Check ◽  
Variable Node ◽  
Power Mode ◽  
Ber Performance

An energy efficient low-density parity-check (LDPC) decoder using an adaptive wordwidth datapath is presented. The decoder switches between a Normal Mode and a reduced wordwidth Low Power Mode. Signal toggling is reduced as variable node processing inputs change in fewer bits. The duration of time that the decoder stays in a given mode is optimized for power and BER requirements and the received SNR. The paper explores different Low Power Mode algorithms to reduce the wordwidth and their implementations. Analysis of the BER performance and power consumption from fixed-point numerical and post-layout power simulations, respectively, is presented for a full parallel 10GBASE-T LDPC decoder in 65 nm CMOS. A 5.10 mm2 low power decoder implementation achieves 85.7 Gbps while operating at 185 MHz and dissipates 16.4 pJ/bit at 1.3 V with early termination. At 0.6 V the decoder throughput is 9.3 Gbps (greater than 6.4 Gbps required for 10GBASE-T) while dissipating an average power of 31 mW. This is 4.6 lower than the state of the art reported power with an SNR loss of 0.35 dB at .

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