scholarly journals LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization

VLSI Design ◽  
2013 ◽  
Vol 2013 ◽  
pp. 1-14 ◽  
Author(s):  
Tinoosh Mohsenin ◽  
Houshmand Shirani-mehr ◽  
Bevan M. Baas
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
State Of The Art ◽  
Average Power ◽  
Parity Check ◽  
Ldpc Decoder ◽  
Low Density Parity Check ◽  
Variable Node ◽  
Power Mode ◽  
Ber Performance

An energy efficient low-density parity-check (LDPC) decoder using an adaptive wordwidth datapath is presented. The decoder switches between a Normal Mode and a reduced wordwidth Low Power Mode. Signal toggling is reduced as variable node processing inputs change in fewer bits. The duration of time that the decoder stays in a given mode is optimized for power and BER requirements and the received SNR. The paper explores different Low Power Mode algorithms to reduce the wordwidth and their implementations. Analysis of the BER performance and power consumption from fixed-point numerical and post-layout power simulations, respectively, is presented for a full parallel 10GBASE-T LDPC decoder in 65 nm CMOS. A 5.10 mm2 low power decoder implementation achieves 85.7 Gbps while operating at 185 MHz and dissipates 16.4 pJ/bit at 1.3 V with early termination. At 0.6 V the decoder throughput is 9.3 Gbps (greater than 6.4 Gbps required for 10GBASE-T) while dissipating an average power of 31 mW. This is 4.6 lower than the state of the art reported power with an SNR loss of 0.35 dB at .

scholarly journals A Low-Complexity Euclidean Orthogonal LDPC Architecture for Low Power Applications

2015 ◽  
Vol 2015 ◽  
pp. 1-8
Author(s):  
M. Revathy ◽  
R. Saravanan
Keyword(s):  
Low Power ◽  
Low Complexity ◽  
Fourth Generation ◽  
Low Density ◽  
Parity Check ◽  
Ldpc Decoder ◽  
Low Density Parity Check ◽  
Variable Node ◽  
High Efficient ◽  
Decoder Architecture

Low-density parity-check (LDPC) codes have been implemented in latest digital video broadcasting, broadband wireless access (WiMax), and fourth generation of wireless standards. In this paper, we have proposed a high efficient low-density parity-check code (LDPC) decoder architecture for low power applications. This study also considers the design and analysis of check node and variable node units and Euclidean orthogonal generator in LDPC decoder architecture. The Euclidean orthogonal generator is used to reduce the error rate of the proposed LDPC architecture, which can be incorporated between check and variable node architecture. This proposed decoder design is synthesized on Xilinx 9.2i platform and simulated using Modelsim, which is targeted to 45 nm devices. Synthesis report proves that the proposed architecture greatly reduces the power consumption and hardware utilizations on comparing with different conventional architectures.

scholarly journals Hardwarearchitektur für einen universellen LDPC Decoder

2009 ◽  
Vol 7 ◽  
pp. 213-218
Author(s):  
C. Beuschel ◽  
H.-J. Pfleiderer
Keyword(s):  
Ldpc Code ◽  
Low Density ◽  
Parity Check ◽  
Wird Eine ◽  
Ldpc Decoder ◽  
Low Density Parity Check

Abstract. Im vorliegenden Beitrag wird eine universelle Decoderarchitektur für einen Low-Density Parity-Check (LDPC) Code Decoder vorgestellt. Anders als bei den in der Literatur häufig beschriebenen Architekturen für strukturierte Codes ist die hier vorgestellte Architektur frei programmierbar, so dass jeder beliebige LDPC Code durch eine Änderung der Initialisierung des Speichers für die Prüfmatrix mit derselben Hardware decodiert werden kann. Die größte Herausforderung beim Entwurf von teilparallelen LDPC Decoder Architekturen liegt im konfliktfreien Datenaustausch zwischen mehreren parallelen Speichern und Berechnungseinheiten, wozu ein Mapping und Scheduling Algorithmus benötigt wird. Der hier vorgestellte Algorithmus stützt sich auf Graphentheorie und findet für jeden beliebigen LDPC Code eine für die Architektur optimale Lösung. Damit sind keine Wartezyklen notwendig und die Parallelität der Architektur wird zu jedem Zeitpunkt voll ausgenutzt.

Energy-Efficient and Area-Efficient QC-LDPC with RS Decoders Using 2M-LMSA

2014 ◽  
Vol 24 (02) ◽  
pp. 1550026 ◽  
Author(s):  
Chang-Kun Yao ◽  
Yun-Ching Tang ◽  
Hongchin Lin
Keyword(s):  
Energy Efficient ◽  
Communication Systems ◽  
Average Power ◽  
Ldpc Code ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Hardware Complexity ◽  
Chip Area ◽  
Ldpc Decoder ◽  
Area Efficient

This study proposes an energy-efficient and area-efficient dual-path low-density parity-check (LDPC) with Reed–Solomon (RS) decoder for communication systems. Hardware complexity is reduced by applying a dual-path 2-bit modified layered min-sum algorithm (2M-LMSA) to a (2550, 2040) quasi-cyclic LDPC (QC-LDPC) code with the column and row weights of 3 and 15, respectively. The simplified check node units (CNUs) reduce memory and routing complexity as well as the energy needed to decode each bit. A throughput of 11 Gb/s is achieved by using 90-nm CMOS technology at a clock frequency of 208 MHz at 0.9 V with average power of 244 mW on a chip area of 3.05 mm2. Decoding performance is further improved by appending the (255, 239) RS decoder after the LDPC decoder. The LDPC plus RS decoder consumes the power of 434 mW on the area of 3.45 mm2.

An Application of LDPC Code for Wireless Coherent-Light Commutation in Atmospheric Channel

2013 ◽  
Vol 347-350 ◽  
pp. 1864-1867
Author(s):  
Ning Hao ◽  
Yang An Zhang ◽  
Jin Nan Zhang ◽  
Ming Lun Zhang ◽  
Xue Guang Yuan
Keyword(s):  
High Speed ◽  
System Simulation ◽  
Ldpc Code ◽  
Low Density ◽  
Parity Check ◽  
Coherent Light ◽  
Line System ◽  
Low Density Parity Check ◽  
Atmospheric Channel ◽  
Ber Performance

Low Density Parity Check code is more and more taken seriously in high-speed transmission. In this article we represent a LDPC coder and decoder which based on IEEE802.16e and realize the coder and decoder with Virtex-5 FPGA. By using Matlab to make an off-line system simulation, we analyzed and compared the LDPC performance under the different length of code for LDPC coder then analyzed the influence of different iteration to the LDPC BER performance of decoder.

scholarly journals Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders

F1000Research ◽  
2022 ◽  
Vol 11 ◽  
pp. 7
Author(s):  
Chinnaiyan Senthilpari ◽  
Rosalind Deena ◽  
Lee Lini
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Computer Aided Design ◽  
Error Correcting Codes ◽  
Low Density ◽  
Parity Check ◽  
Low Density Parity Check ◽  
Low Power Dissipation ◽  
Pass Transistor ◽  
Pass Transistor Logic

Background: Low-density parity-check (LDPC) codes are more error-resistant than other forward error-correcting codes. Existing circuits give high power dissipation, less speed, and more occupying area. This work aimed to propose a better design and performance circuit, even in the presence of noise in the channel. Methods: In this research, the design of the multiplexer and demultiplexer were achieved using pass transistor logic. The target parameters were low power dissipation, improved throughput, and more negligible delay with a minimum area. One of the essential connecting circuits in a decoShder architecture is a multiplexer (MUX) and a demultiplexer (DEMUX) circuit. The design of the MUX and DEMUX contributes significantly to the performance of the decoder. The aim of this paper was the design of a 4 × 1 MUX to route the data bits received from the bit update blocks to the parallel adder circuits and a 1 × 4 DEMUX to receive the input bits from the parallel adder and distribute the output to the bit update blocks in a layered architecture LDPC decoder. The design uses pass transistor logic and achieves the reduction of the number of transistors used. The proposed circuit was designed using the Mentor Graphics CAD tool for 180 nm technology. Results: The parameters of power dissipation, area, and delay were considered crucial parameters for a low power decoder. The circuits were simulated using computer-aided design (CAD) tools, and the results depicted a significantly low power dissipation of 7.06 nW and 5.16 nW for the multiplexer and demultiplexer, respectively. The delay was found to be 100.5 ns (MUX) and 80 ns (DEMUX). Conclusion: This decoder’s potential use may be in low-power communication circuits such as handheld devices and Internet of Things (IoT) circuits.

An Efficient VLSI Architecture for Nonbinary LDPC Decoder with Adaptive Message Control

2015 ◽  
Vol 4 (1) ◽  
pp. 6
Author(s):  
Varatharajan Ramachandran
Keyword(s):  
Power Consumption ◽  
Vlsi Architecture ◽  
Ldpc Codes ◽  
Parity Check ◽  
Decoding Complexity ◽  
Ldpc Decoder ◽  
Message Length ◽  
Low Density Parity Check ◽  
Decoder Architecture ◽  
Memory Accesses

<p>A new decoder architecture for nonbinary low-density parity check (LDPC) codes is presented in this paper to reduce the hardware operational complexity and power consumption. Adaptive message control (AMC) is to achieve the low decoding complexity,  that dynamically trims the message length of belief information to reduce the amount of memory accesses and arithmetic operations. A new horizontal nonbinary LDPC decoder architecture is developed to implement AMC. Key components in the architecture have been designed with the consideration of variable message lengths to leverage the benefit of the proposed AMC. Simulation results demonstrate that the proposed nonbinary LDPC decoder architecture can significantly reduce hardware operations and power consumption as compared with existing work with negligible performance degradation.</p>

scholarly journals ONE-MINIUM-ONLY BASIC-SET TRELLIS MIN-MAX DECODER ARCHITECTURE FOR NONBINARY LDPC CODE

2021 ◽  
Vol 37 (2) ◽  
pp. 91-106
Author(s):  
The Cuong Dinh ◽  
Huyen Pham Thi ◽  
Hung Dao Tuan ◽  
Nghia Pham Xuan
Keyword(s):  
State Of The Art ◽  
Ldpc Code ◽  
Galois Field ◽  
Cmos Technology ◽  
Parity Check ◽  
High Complexity ◽  
Variable Node ◽  
Basic Set ◽  
Decoder Architecture ◽  
Check Node

Nonbinary low-density-parity-check (NB-LDPC) code outperforms their binary counterpart in terms of error-correcting performance and error-floor property when the code length is moderate. However, the drawback of NB-LDPC decoders is high complexity and the complexity increases considerably when increasing the Galois-field order. In this paper, an One-Minimum-Only basic-set trellis min-max (OMO-BS-TMM) algorithm and the corresponding decoder architecture are proposed for NBLDPC codes to greatly reduce the complexity of the check node unit (CNU) as well as the whole decoder. In the proposed OMO-BS-TMM algorithm, only the first minimum values are used for generating the check node messages instead of using both the first and second minimum values, and the number of messages exchanged between the check node and the variable node is reduced in comparison with the previous works. Layered decoder architectures based on the proposed algorithm were implemented for the (837, 726) NB-LDPC code over GF(32) using 90-nm CMOS technology. The implementation results showed that the OMO-BS-TMM algorithm achieves the almost similar error-correcting performance, and a reduction of the complexity by 31.8% and 20.5% for the whole decoder, compared to previous works. Moreover, the proposed decoder achieves a higher throughput at 1.4 Gbps, compared with the other state-of-the-art NBLDPC decoders.

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