scholarly journals Tip- and Laser-based 3D Nanofabrication in Extended Macroscopic Working Areas

2021 ◽  
Author(s):  
Ingo Ortlepp ◽  
Thomas Fröhlich ◽  
Roland Füßl ◽  
Johann Reger ◽  
Christoph Schäffel ◽  
...  
Keyword(s):  
High Performance ◽  
Semiconductor Industry ◽  
Life Sciences ◽  
Basic Research ◽  
Paradigm Change ◽  
Proof Of Concept ◽  
Custom Design ◽  
Global Companies ◽  
20 Nm ◽  
Intense Research

AbstractThe field of optical lithography is subject to intense research and has gained enormous improvement. However, the effort necessary for creating structures at the size of 20 nm and below is considerable using conventional technologies. This effort and the resulting financial requirements can only be tackled by few global companies and thus a paradigm change for the semiconductor industry is conceivable: custom design and solutions for specific applications will dominate future development (Fritze in: Panning EM, Liddle JA (eds) Novel patterning technologies. International society for optics and photonics. SPIE, Bellingham, 2021. 10.1117/12.2593229). For this reason, new aspects arise for future lithography, which is why enormous effort has been directed to the development of alternative fabrication technologies. Yet, the technologies emerging from this process, which are promising for coping with the current resolution and accuracy challenges, are only demonstrated as a proof-of-concept on a lab scale of several square micrometers. Such scale is not adequate for the requirements of modern lithography; therefore, there is the need for new and alternative cross-scale solutions to further advance the possibilities of unconventional nanotechnologies. Similar challenges arise because of the technical progress in various other fields, realizing new and unique functionalities based on nanoscale effects, e.g., in nanophotonics, quantum computing, energy harvesting, and life sciences. Experimental platforms for basic research in the field of scale-spanning nanomeasuring and nanofabrication are necessary for these tasks, which are available at the Technische Universität Ilmenau in the form of nanopositioning and nanomeasuring (NPM) machines. With this equipment, the limits of technical structurability are explored for high-performance tip-based and laser-based processes for enabling real 3D nanofabrication with the highest precision in an adequate working range of several thousand cubic millimeters.

scholarly journals High performance, electroforming-free, thin film memristors using ionic Na0.5Bi0.5TiO3

2021 ◽  
Vol 9 (13) ◽  
pp. 4522-4531
Author(s):  
Chao Yun ◽  
Matthew Webb ◽  
Weiwei Li ◽  
Rui Wu ◽  
Ming Xiao ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Films ◽  
Resistive Switching ◽  
Growth Temperature ◽  
High Performance ◽  
20 Nm

Interfacial resistive switching and composition-tunable RLRS are realized in ionically conducting Na0.5Bi0.5TiO3 thin films, allowing optimised ON/OFF ratio (>104) to be achieved with low growth temperature (600 °C) and low thickness (<20 nm).

High performance continuously tunable top-emitting vertical cavity laser with 20 nm wavelength range

1997 ◽  
Vol 33 (12) ◽  
pp. 1051 ◽  
Author(s):  
M.Y. Li ◽  
W. Yuen ◽  
G.S. Li ◽  
C.J. Chang-Hasnain
Keyword(s):  
Wavelength Range ◽  
High Performance ◽  
Cavity Laser ◽  
20 Nm ◽  
Vertical Cavity

New RP-CVD grown ultra-high performance selectively B-doped pure-Ge 20 nm QWs on (100)Si as basis material for post-Si CMOS technology

2013 ◽  
Vol 11 (1) ◽  
pp. 61-64 ◽  
Author(s):  
O. A. Mironov ◽  
A. H. A. Hassan ◽  
M. Uhlarz ◽  
S. Kiatgamolchai ◽  
A. Dobbie ◽  
...  
Keyword(s):  
High Performance ◽  
Cmos Technology ◽  
Basis Material ◽  
20 Nm

Ion Beam Lithography And Resist Processing for Nanofabrication

2006 ◽  
Vol 983 ◽  
Author(s):  
Khalil Arshak ◽  
Stephen F. Gilmartin ◽  
Damien Collins ◽  
Olga Korostynska ◽  
Arousian Arshak ◽  
...  
Keyword(s):  
Nanoimprint Lithography ◽  
Ion Beam ◽  
Semiconductor Industry ◽  
Device Fabrication ◽  
Proximity Effects ◽  
Process Equipment ◽  
Proof Of Concept ◽  
Profile Control ◽  
Wafer Processing ◽  
O2 Plasma

AbstractThe International Technology Roadmap for Semiconductors (ITRS) identifies the shrinking of lithography critical dimensions (CDs) as one of biggest challenges facing the semiconductor industry as it progresses to smaller geometry nodes. Nanolithography, the patterning of masking CDs below 100nm, enables both nanoscale wafer processing and the exploration of novel nanotechnology applications and devices.Focused Ion Beam (FIB) lithography has significant advantages over alternative nanolithography techniques, particularly when comparing resist sensitivity, topography effects, proximity effects and backscattering. FIB lithography uses the implantation of ions, such as Ga+, in its masking process. Ions implanted into resist in this manner typically have shallow penetration depths (<100nm for Ga+), and this would typically require the use of very thin resist layers during processing. This is often incompatible with subsequent fabrication steps such as plasma etching, where thicker resist layers are usually required to facilitate etch selectivity. Top surface imaging (TSI) is a solution to this problem.When compared with conventional microelectronic lithography, nanolithography techniques such as EUV, electron beam and nanoimprint lithography require expensive process equipment and the use of non-standard process materials.The 2-step negative resist image by dry etching (2-step NERIME) process is a FIB TSI scheme developed for DNQ/novolak based resists, and involves FIB exposure of resist with Ga+, followed by O2 plasma dry development using reactive ion etching. The 2-step NERIME process uses equipment sets and materials commonly found in microelectronic device fabrication (FIB tool, O2 plasma etcher, DNQ/novolak resists), and provides a low-cost and convenient nanolithography option for proof-of-concept nanoscale processing.To be of practical use, a nanolithography scheme must be capable of patterning nanoscale resist features over substrate topography while retaining resist profile control. The nanolithography scheme must also integrate with subsequent plasma etch processing steps that etch various material films such as metals, Si, SiO2, SiN. The 2-step NERIME FIB TSI process has been used to successfully pattern nanoscale (40nm-90nm) resist features on planar and topography substrates. We have also demonstrated sub-100nm etched features on topography substrates using the 2-step NERIME process, reporting 80nm Polycide and TiN etched features, and 90nm Ti etched features, that exhibit excellent profiles and minimal line edge roughness (LER).It is expected that the 2-step NERIME FIB TSI process will be further extended to etch sub-40nm features over topography substrates. The nanoscale etched features will be used to explore proof-of-concept geometry shrink & novel structures, with many possible applications, including NEMs and nanosensors research and development.

Advances in Fine Pitch Off-Chip Interconnections Through the Use of a Novel Surface Finish

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 001531-001563
Author(s):  
Arnd Kilian ◽  
Gustavo Ramos ◽  
Rick Nichols ◽  
Robin Taylor ◽  
Vanessa Smet ◽  
...  
Keyword(s):  
Low Temperature ◽  
Surface Finish ◽  
System Integration ◽  
High Performance ◽  
Semiconductor Industry ◽  
Electroless Nickel ◽  
Interfacial Stress ◽  
Copper Oxidation ◽  
Fine Pitch ◽  
Metallurgical Bond

One constant in electronic system integration is the continuous trend towards smaller devices with increased functionality, driven by emerging mobile and high-performance applications. This brings the need for higher bandwidth at lower power, translating into increased I/O density, to enable highly-integrated systems with form factor reduction. These requirements result in the necessity of interconnection pitch-scaling, below 30 μm in the near future, and substrates with high wiring densities, leading to routing with sub 5 μm L/S where standard surface finishes (ENIG, ENEPIG) are no longer applicable. Copper pillar with solder caps technology is currently the prevalent solution for off-chip interconnections at fine pitch, dominating the high performance and mobile market with pitches as low as 40 μm in production. However, this technology faces many fundamental limitations in pitch scaling below 30 μm, due to solder bridging, IMC-solder interfacial stress management, and poor power handling capability of solders. All-copper interconnections without solder are very sought after by the semiconductor industry and have been applied to 3D-IC stacking, however no cost effective, manufacturable and scalable solution has been proposed to date for HVM and application to non CTE matched package structures. The low temperature Cu-Cu interconnection technology without solder recently patented by Georgia Tech PRC is one of the most promising solutions to this problem. The main bottleneck of copper oxidation is dealt with by application of ENIG on the Cu bumps and pads, enabling formation of a reliable metallurgical bond by thermocompression bonding (TCB) at temperatures below 200°C, in air, with cycle-times compatible with HVM targets. However, to ensure a bump collapse of 3 μm to overcome non-coplanarities and warpage, a pressure of 300MPa is used in the Process-of-Record (PoR) conditions, limiting the scalability of this technology. This paper introduces a novel Electroless Palladium / Autocatalytic Gold (EPAG) surface finish process, to enable the next generation of high density substrates and interconnections. With circa 100nm-thin Pd and Au layers, the EPAG finish can be applied to fine L/S wiring, with no risk of bridging adjacent Cu traces, even with spacing below 5 μm. Further, the EPAG finish is compatible with current interconnection processes; such as wire bonding, and the Cu pillar and solder cap technology for fine-pitch applications. For further pitch reduction, the EPAG surface finish was coupled to GT PRC's low-temperature Cu-interconnections, in an effort to reduce the bonding load for enhanced manufacturability without degrading the metallurgical bond or reliability. This paper is the first demonstration of such interconnections. The effect of the surface finish thickness and composition on the bonding load, assembly yield, quality of the metallurgical bond was extensively evaluated based on analysis of the metal interface microstructures and the chemical composition of the joints. The current PoR using Electroless Nickel / Immersion Gold (ENIG) coated Cu pillars and pads was used as reference. A novel surface finish is introduced, which allows formation of Cu-Cu interconnections without solder at lower pressure, between a silicon die and glass, organic or silicon substrate at fine pitch, allowing the performance improvements demanded by the IC Packaging Industry.

Understanding Mold Compound Behavior on Flip Chip QFN Packages

2018 ◽  
Vol 2018 (1) ◽  
pp. 000125-000128
Author(s):  
Ruby Ann M. Camenforte ◽  
Jason Colte ◽  
Richard Sumalinog ◽  
Sylvester Sanchez ◽  
Jaimal Williamson
Keyword(s):  
Thermal Performance ◽  
High Performance ◽  
Flip Chip ◽  
Low Cost ◽  
Semiconductor Industry ◽  
Gelation Time ◽  
Molding Process ◽  
Design Quality ◽  
Low Resistance ◽  
Die Attach

Abstract Overmolded Flip Chip Quad Flat No-lead (FCQFN) is a low cost flip chip on leadframe package where there is no need for underfill, and is compatible with Pb free or high Pb metallurgy. A robust leadframe design, quality solder joint formation and an excellent molding process are three factors needed to assemble a high performance FCQFN. It combines the best of both wirebonded QFN and wafer chip scale devices. For example, wafer chip scale has low resistance, but inadequate thermal performance (due to absence of thermal pad), whereas wirebonded QFN has good thermal performance (i.e., heat dissipated through conductive die attach material, through the pad and to the board) but higher resistance. Flip chip QFN combines both positive aspects – that is: low resistance and good thermals. One of the common defects for molded packages across the semiconductor industry is the occurrence of mold voiding as this can potentially affect the performance of a device. This paper will discuss how mold voiding is mitigated by understanding the mold compound behavior on flip chip QFN packages. Taking for example the turbulent mold flow observed on flip chip QFN causing mold voids. Mold compound material itself has a great contribution to mold voids, hence defining the correct attributes of the mold compound is critical. Altering the mold compound property to decrease the mold compound rheology is a key factor. This dynamic interaction between mold compound and flip chip QFN package configuration is the basis for a series of design of experiments using a full factorial matrix. Key investigation points are establishing balance in mold compound chemistry allowing flow between bump pitch, as well as the mold compound rheology, where gelation time has to be properly computed to allow flow across the leadframe. Understanding the flow-ability of mold compound for FCQFN, the speed of flow was optimized to check on its impact on mold voids. Mold airflow optimization is also needed to help fill in tighter bump spacing but vacuum-on time needs to be optimized as well.

scholarly journals High Performance GAA SNWT with a Triangular Cross Section: Simulation and Experiments

2018 ◽  
Vol 8 (9) ◽  
pp. 1553 ◽  
Author(s):  
Ming Li ◽  
Gong Chen ◽  
Ru Huang
Keyword(s):  
Cross Section ◽  
High Performance ◽  
Silicon Nanowire ◽  
Wet Etching ◽  
Excellent Performance ◽  
Cross Sectional ◽  
Triangular Cross Section ◽  
Tcad Simulation ◽  
Equivalent Distance ◽  
20 Nm

In this paper, we present a gate-all-around silicon nanowire transistor (GAA SNWT) with a triangular cross section by simulation and experiments. Through the TCAD simulation, it was found that with the same nanowire width, the triangular cross-sectional SNWT was superior to the circular or quadrate one in terms of the subthreshold swing, on/off ratio, and SCE immunity, which resulted from the smallest equivalent distance from the nanowire center to the surface in triangular SNWTs. Following this, we fabricated triangular cross-sectional GAA SNWTs with a nanowire width down to 20 nm by TMAH wet etching. This process featured its self-stopped etching behavior on a silicon (1 1 1) crystal plane, which made the triangular cross section smooth and controllable. The fabricated triangular SNWT showed an excellent performance with a large Ion/Ioff ratio (~107), low SS (85 mV/dec), and preferable DIBL (63 mV/V). Finally, the surface roughness mobility of the fabricated device at a low temperature was also extracted to confirm the benefit of a stable cross section.

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