Understanding Mold Compound Behavior on Flip Chip QFN Packages

2018 ◽  
Vol 2018 (1) ◽  
pp. 000125-000128
Author(s):  
Ruby Ann M. Camenforte ◽  
Jason Colte ◽  
Richard Sumalinog ◽  
Sylvester Sanchez ◽  
Jaimal Williamson
Keyword(s):  
Thermal Performance ◽  
High Performance ◽  
Flip Chip ◽  
Low Cost ◽  
Semiconductor Industry ◽  
Gelation Time ◽  
Molding Process ◽  
Design Quality ◽  
Low Resistance ◽  
Die Attach

Abstract Overmolded Flip Chip Quad Flat No-lead (FCQFN) is a low cost flip chip on leadframe package where there is no need for underfill, and is compatible with Pb free or high Pb metallurgy. A robust leadframe design, quality solder joint formation and an excellent molding process are three factors needed to assemble a high performance FCQFN. It combines the best of both wirebonded QFN and wafer chip scale devices. For example, wafer chip scale has low resistance, but inadequate thermal performance (due to absence of thermal pad), whereas wirebonded QFN has good thermal performance (i.e., heat dissipated through conductive die attach material, through the pad and to the board) but higher resistance. Flip chip QFN combines both positive aspects – that is: low resistance and good thermals. One of the common defects for molded packages across the semiconductor industry is the occurrence of mold voiding as this can potentially affect the performance of a device. This paper will discuss how mold voiding is mitigated by understanding the mold compound behavior on flip chip QFN packages. Taking for example the turbulent mold flow observed on flip chip QFN causing mold voids. Mold compound material itself has a great contribution to mold voids, hence defining the correct attributes of the mold compound is critical. Altering the mold compound property to decrease the mold compound rheology is a key factor. This dynamic interaction between mold compound and flip chip QFN package configuration is the basis for a series of design of experiments using a full factorial matrix. Key investigation points are establishing balance in mold compound chemistry allowing flow between bump pitch, as well as the mold compound rheology, where gelation time has to be properly computed to allow flow across the leadframe. Understanding the flow-ability of mold compound for FCQFN, the speed of flow was optimized to check on its impact on mold voids. Mold airflow optimization is also needed to help fill in tighter bump spacing but vacuum-on time needs to be optimized as well.

High Reliability and Thermal Performance FCBGA Package

2007 ◽  
Author(s):  
Gino Hung ◽  
Ho-Yi Tsai ◽  
Chun An Huang ◽  
Steve Chiu ◽  
C. S. Hsiao
Keyword(s):  
Thermal Performance ◽  
High Performance ◽  
Flip Chip ◽  
Dielectric Material ◽  
High Reliability ◽  
Lead Free ◽  
Molding Process ◽  
Molding Compound ◽  
Reliability Performance ◽  
Low K

A high reliability and high thermal performance molding flip chip ball grid arrays structure which was improved from Terminator FCBGA®. (The structure are shown as Fig. 1) It has many advantages, like better coplanarity, high through put (multi pes for each shut of molding process), low stress, and high thermal performance. In conventional flip chip structure, underfill dispenses and cure processes are a bottleneck due to low through put (dispensing unit by unit). For the high performance demand, large package/die size with more integrated functions needs to meet reliability criteria. Low k dielectric material, lead free bump especially and the package coplanarity are also challenges for package development. Besides, thermal performance is also a key concern with high power device. From simulation and reliability data, this new structure can provide strong bump protection and reach high reliability performance and can be applied for low-K chip and all kind of bump composition such as tin-lead, high lead, and lead free. Comparing to original Terminator FCBGA®, this structure has better thermal performance because the thermal adhesive was added between die and heat spreader instead of epoxy molding compound (EMC). The thermal adhesive has much better thermal conductivity than EMC. Furthermore, this paper also describes the process and reliability validation result.

COMPARISON OF FOWLP VS QFN PACKAGE FROM THERMAL ASPECT

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 000248-000271 ◽  
Author(s):  
Qun Wan
Keyword(s):  
Thermal Performance ◽  
Flip Chip ◽  
Low Cost ◽  
Wafer Level ◽  
Element Analysis ◽  
Rf Power Amplifier ◽  
Thermal Test ◽  
Die Attach ◽  
Bottleneck Identification ◽  
Resistance Breakdown

The QFN package dominates IC industry with a small number of IOs due to its simplicity, maturity and low cost in mass production. However, as the industry progresses toward portability and smaller size, thinner and more compact packages such as Fan Out Wafer Level Package (FOWLP) is a better option/solution than QFN package. Due to its flip chip configuration, imbedded redistribution (RDL) interconnection and elimination of die attach layer, the FOWLP package has potential to surpass QFN package in thermal performance. This paper utilized a typical 3-stage RF power amplifier die as a thermal test vehicle, packaged with FOWLP and QFN, built FEA (Finite Element Analysis) thermal models and analyzed the thermal performance by thermal resistance breakdown and thermal bottleneck identification. Comparison of FOWLP and QFN shows that the heat paths and bottlenecks within each package are quite different. In QFN package, bottleneck lies in the die attach layer while in FOWLP package, it lies in the backend layers on the die and the RDL vias. FOWLP package may also require better thermal vias performance in PCB due to smaller footprint of LGA/Solder. Large horizontal heat spreading in a poorly design PCB may offset the thermal advantages in FOWLP package. The simulation results of both packages have good correlation with Infrared (IR) measurement of corresponding thermal test vehicles.

Thermosonic Gold to Gold Intermetallic Advantages for CSP Packaging

2010 ◽  
Vol 2010 (1) ◽  
pp. 000821-000828
Author(s):  
Philip Couts
Keyword(s):  
Thermal Performance ◽  
High Performance ◽  
Flip Chip ◽  
Bonding Temperature ◽  
High Growth ◽  
Consumer Products ◽  
Color Temperature ◽  
Solder Alloys ◽  
Assembly Method ◽  
Die Attach

Flip chip thermosonic back end assembly method is a low cost clean gold to gold interconnection method. The advancement of flip chip thermosonic process for CSP packaging of HBLED and CMOS image sensors is occurring due to the precision intermetallic clean interconnection properties and ability to provide a small form factor packaging to consumer products. This paper will investigate thermosonic metal to metal interconnection process for these high growth assembly markets. Thermosonic bonding uses a micro weld interconnection die attach method at lower bonding temperature (150°C). The thermosonic metal to metal interconnection method is lead free and the process does not use flux or solder alloys. Thermosonic flip chip die attach process uses a robust individual die “scrubbing” process which reduces assembly steps and eliminates the mass reflow oven used commonly in C4 solder process. The metal to metal interconnection method provides excellent thermal performance for HBLEDs which require the Tj peak temperature to be controlled to maximize device MTBF and overall color temperature performance. The uses of metal to metal interconnection method provide superior thermal performance when compared to solder alloys. The metal to metal interconnection method provides high precision with low particle generation for high performance bonding of CMOS image die using a low-k dielectric wafer. The line spacing for the substrate is 50 μm / 50 μm. Stud bumping machines have a ball placement accuracy of +/− 2.5 μm. Thermosonic GGI die bonders have a mounting accuracy of +/−7 μm. Thermosonic bonding has fast process bonding times of < 500 msec which is important productivity factor in cost sensitive cell phone camera and flash modules.

Creating Semiconductor Value through Advanced Package Technology

2016 ◽  
Vol 2016 (S1) ◽  
pp. S1-S46
Author(s):  
Ron Huemoeller
Keyword(s):  
Big Five ◽  
Flip Chip ◽  
Microelectromechanical Systems ◽  
Technology Innovation ◽  
Low Cost ◽  
Semiconductor Industry ◽  
Significant Shift ◽  
Wafer Level ◽  
Chip Scale Package ◽  
Advanced Packaging

Over the past few years, there has been a significant shift from PCs and notebooks to smartphones and tablets as drivers of advanced packaging innovation. In fact, the overall packaging industry is doing quite well today as a result, with solid growth expected to create a market value in excess of $30B USD by 2020. This is largely due to the technology innovation in the semiconductor industry continuing to march forward at an incredible pace, with silicon advancements in new node technologies continuing on one end of the spectrum and innovative packaging solutions coming forward on the other in a complementary fashion. The pace of innovation has quickened as has the investments required to bring such technologies to production. At the packaging level, the investments required to support the advancements in silicon miniaturization and heterogeneous integration have now reached well beyond $500M USD per year. Why has the investment to support technology innovation in the packaging community grown so much? One needs to look no further than the complexity of the most advanced package technologies being used today and coming into production over the next year. Advanced packaging technologies have increased in complexity over the years, transitioning from single to multi-die packaging, enabled by 3-dimensional integration, system-in-package (SiP), wafer-level packaging (WLP), 2.5D/3D technologies and creative approached to embedding die. These new innovative packaging technologies enable more functionality and offer higher levels of integration within the same package footprint, or even more so, in an intensely reduced footprint. In an industry segment that has grown accustomed to a multitude of package options, technology consolidation seems evident, producing “The Big Five” advanced packaging platforms. These include low-cost flip chip, wafer-level chip-scale package (WLCSP), microelectromechanical systems (MEMS), laminate-based advanced system-in-package (SiP) and wafer-based advanced SiP designs. This presentation will address ‘The Big Five’ packaging platforms and how they are adding value to the Semiconductor Industry.

scholarly journals Interactive Q-Learning Approach for Pick-and-Place Optimization of the Die Attach Process in the Semiconductor Industry

2019 ◽  
Vol 2019 ◽  
pp. 1-8 ◽  
Author(s):  
Gilseung Ahn ◽  
Myunghwan Park ◽  
You-Jin Park ◽  
Sun Hur
Keyword(s):  
High Performance ◽  
Semiconductor Industry ◽  
Search Time ◽  
Generalization Ability ◽  
Q Learning ◽  
Die Attach ◽  
Metaheuristic Methods ◽  
Pick And Place ◽  
Novel Method ◽  
And Performance

In semiconductor back-end production, the die attach process is one of the most critical steps affecting overall productivity. Optimization of this process can be modeled as a pick-and-place problem known to be NP-hard. Typical approaches are rule-based and metaheuristic methods. The two have high or low generalization ability, low or high performance, and short or long search time, respectively. The motivation of this paper is to develop a novel method involving only the strengths of these methods, i.e., high generalization ability and performance and short search time. We develop an interactive Q-learning in which two agents, a pick agent and a place agent, are trained and find a pick-and-place (PAP) path interactively. From experiments, we verified that the proposed approach finds a shorter path than the genetic algorithm given in previous research.

Next-Generation Copper, Nickel and Lead-Free Metallization Products for Next-Generation Devices and Applications

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 000611-000638
Author(s):  
Jonathan Prange ◽  
Yi Qin ◽  
Matthew Thorseth ◽  
Inho Lee ◽  
Masaaki Imanari ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Low Cost ◽  
Lead Free ◽  
Lead Free Solder ◽  
Next Generation ◽  
Copper Nickel ◽  
Microelectronic Devices ◽  
Architectural Features ◽  
Free Solder

Flip-chip interconnect and 3-D packaging applications must utilize reliable, high-performance metallization products in order to produce highly-efficient, low-cost microelectronic devices. As the market moves to shrinking device architectural features and increasingly difficult pattern layouts, more demand is placed on the plating performance of the copper, nickel and lead-free solder products used to create these interconnects. Additionally, the move from traditional C4 bumping processes with lead-free solder to capping processes utilizing copper pillars with lead-free solder requires metal interfaces that are highly compatible in order to avoid defects that could occur. In this paper, next-generation products developed for copper pillar, nickel barrier, and lead-free solder plating will be introduced that are capable of delivering high-performance and highly reliable metallic interconnects. The additive packages that were selected and optimized allowing for increased rate of electrodeposition, uniform height control with controllable pillar shape and smooth surface morphology will be discussed. Furthermore, compatibility will be shown for a lead-free solder cap electrodeposited onto copper pillar structures, both with and without nickel barrier layers, on large pore features (≥50 μm diameter) and micro pore features (≤20 μm diameter) for both bumping and capping applications.

scholarly journals High Performance of Solar Cooker by Heat Transfer Mode Condition System Using Fuzzy Logic Controller Applications

2018 ◽  
Vol 7 (4.10) ◽  
pp. 278 ◽  
Author(s):  
Bhavani S ◽  
Shanmugan. S ◽  
Selvaraju P
Keyword(s):  
Heat Transfer ◽  
Fuzzy Logic ◽  
Thermal Performance ◽  
System Performance ◽  
High Performance ◽  
Fuzzy Logic Controller ◽  
High Efficiency ◽  
Low Cost ◽  
Heat Transfer Mode ◽  
Transfer Mode

In this work has been made to predict the effect of several parameters on the productivity to a system by expending fuzzy set technique. A solar cooker has been developed low cost and critically high efficiency produce in Vel Tech Multitech Engineering College at Chennai, Tamilnadu, India. Dissects in thermal performance of cooking system have been produced heat transfer follow in fuzzy logic techniques (Low, Medium, and High). The thermal effect of factor should be developed in fuzzy logic for the system. They should have groups of heat transfer produced in fuzzy logic controller for solar cooker system which had been implemented of system performance discussed. It is to study have induced to give the shortly time for the enhancement of the box solar cooker production.  

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