Impact of interface trap charge and temperature on the performance of epitaxial layer tunnel field effect tansistor

2021 ◽  
pp. 105348
Author(s):  
Radhe Gobinda Debnath ◽  
Srimanta Baishya
Keyword(s):  
Epitaxial Layer ◽  
Field Effect ◽  
Interface Trap ◽  
Trap Charge

scholarly journals Metal oxide-graphene field-effect transistor: interface trap density extraction model

2016 ◽  
Vol 7 ◽  
pp. 1368-1376 ◽  
Author(s):  
Faraz Najam ◽  
Kah Cheong Lau ◽  
Cheng Siong Lim ◽  
Yun Seop Yu ◽  
Michael Loong Peng Tan
Keyword(s):  
Surface Potential ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Current Model ◽  
Drain Current ◽  
Interface Trap ◽  
Accurate Calculation ◽  
Trap Charge ◽  
Graphene Field Effect Transistor ◽  
Effect Transistor

A simple to implement model is presented to extract interface trap density of graphene field effect transistors. The presence of interface trap states detrimentally affects the device drain current–gate voltage relationship I ds–V gs. At the moment, there is no analytical method available to extract the interface trap distribution of metal-oxide-graphene field effect transistor (MOGFET) devices. The model presented here extracts the interface trap distribution of MOGFET devices making use of available experimental capacitance–gate voltage C tot–V gs data and a basic set of equations used to define the device physics of MOGFET devices. The model was used to extract the interface trap distribution of 2 experimental devices. Device parameters calculated using the extracted interface trap distribution from the model, including surface potential, interface trap charge and interface trap capacitance compared very well with their respective experimental counterparts. The model enables accurate calculation of the surface potential affected by trap charge. Other models ignore the effect of trap charge and only calculate the ideal surface potential. Such ideal surface potential when used in a surface potential based drain current model will result in an inaccurate prediction of the drain current. Accurate calculation of surface potential that can later be used in drain current model is highlighted as a major advantage of the model.

Subthreshold Degradation of Gate-all-Around Silicon Nanowire Field-Effect Transistors: Effect of Interface Trap Charge

2011 ◽  
Vol 32 (9) ◽  
pp. 1179-1181 ◽  
Author(s):  
B. H. Hong ◽  
N. Cho ◽  
S. J. Lee ◽  
Y. S. Yu ◽  
L. Choi ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Silicon Nanowire ◽  
Interface Trap ◽  
Trap Charge

scholarly journals Interface Trap-Induced Temperature Dependent Hysteresis and Mobility in β-Ga2O3 Field-Effect Transistors

Nanomaterials ◽  
2021 ◽  
Vol 11 (2) ◽  
pp. 494
Author(s):  
Youngseo Park ◽  
Jiyeon Ma ◽  
Geonwook Yoo ◽  
Junseok Heo
Keyword(s):  
Gallium Oxide ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Gate Insulator ◽  
Interface Trap ◽  
Gate Bias ◽  
Temperature Dependent ◽  
Trap Charge ◽  
Time Constants ◽  
Channel Mobility

Interface traps between a gate insulator and beta-gallium oxide (β-Ga2O3) channel are extensively studied because of the interface trap charge-induced instability and hysteresis. In this work, their effects on mobility degradation at low temperature and hysteresis at high temperature are investigated by characterizing electrical properties of the device in a temperature range of 20–300 K. As acceptor-like traps at the interface are frozen below 230 K, the hysteresis becomes negligible but simultaneously the channel mobility significantly degrades because the inactive neutral traps allow additional collisions of electrons at the interface. This is confirmed by the fact that a gate bias adversely affects the channel mobility. An activation energy of such traps is estimated as 170 meV. The activated trap charges’ trapping and de-trapping processes in response to the gate pulse bias reveal that the time constants for the slow and fast processes decrease due to additionally activated traps as the temperature increases.

scholarly journals Interface trap density and mobility extraction in InGaAs buried quantum well metal-oxide-semiconductor field-effect-transistors by gated Hall method

2014 ◽  
Vol 104 (13) ◽  
pp. 131605 ◽  
Author(s):  
Thenappan Chidambaram ◽  
Dmitry Veksler ◽  
Shailesh Madisetti ◽  
Andrew Greene ◽  
Michael Yakimov ◽  
...  
Keyword(s):  
Quantum Well ◽  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Trap Density ◽  
Oxide Semiconductor ◽  
Interface Trap Density ◽  
Interface Trap ◽  
Hall Method

Interface Trap Charge Effects of Monolithic 3D Junctionless Field-Effect Transistors (JLFET) Inverter

2021 ◽  
Vol 21 (8) ◽  
pp. 4252-4257
Author(s):  
Tae Jun Ahn ◽  
Yun Seop Yu
Keyword(s):  
Computer Aided Design ◽  
Field Effect Transistors ◽  
Three Dimensional ◽  
Interface Trap ◽  
Charge Effects ◽  
Trap Charge ◽  
Interlayer Dielectric ◽  
Threshold Voltages ◽  
Propagation Delays ◽  
Aided Design

We investigated the effect of the interface trap charge in a monolithic three-dimensional inverter structure composing of JLFETs (M3DINV-JLFET), using the interface trap charge distribution extracted in the previous study. The effect of interface trap charge was compared with a conventional M3DINV composing of MOSFETs (M3DINV-MOSFETs) by technology computer-aided design simulation. When the interface trap charges in both M3DINV-JLFET and M3DINV-MOSFET are added, the threshold voltages, on-current levels, and subthreshold swings of both JLFETs and MOSFETs increase, decrease, and increase, respectively, and switching voltages and propagation delays of M3DINV are shifted and increased, respectively. However, since JLFET and MOSFET have different current paths of bulk and interface in channel, respectively, MOSFET is more affected by the interface trap, and M3DINV-JLFET has almost less effect of interface trap at different thickness of interlayer dielectric, compared to M3DINV-MOSFET.

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