Subthreshold Degradation of Gate-all-Around Silicon Nanowire Field-Effect Transistors: Effect of Interface Trap Charge

2011 ◽  
Vol 32 (9) ◽  
pp. 1179-1181 ◽  
Author(s):  
B. H. Hong ◽  
N. Cho ◽  
S. J. Lee ◽  
Y. S. Yu ◽  
L. Choi ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Silicon Nanowire ◽  
Interface Trap ◽  
Trap Charge

scholarly journals Simulation studies on electrical characteristics of silicon nanowire feedback field-effect transistors with interface trap charges

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Yejin Yang ◽  
Young-Soo Park ◽  
Jaemin Son ◽  
Kyoungah Cho ◽  
Sangsig Kim
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Silicon Nanowire ◽  
Drain Current ◽  
Memory Window ◽  
Interface Trap ◽  
Electrical Characteristics ◽  
The Difference ◽  
Trap Charges

AbstractIn this study, we examine the electrical characteristics of silicon nanowire feedback field-effect transistors (FBFETs) with interface trap charges between the channel and gate oxide. The band diagram, I–V characteristics, memory window, and operation were analyzed using a commercial technology computer-aided design simulation. In an n-channel FBFET, the memory window narrows (widens) from 5.47 to 3.59 V (9.24 V), as the density of the positive (negative) trap charges increases. In contrast, in the p-channel FBFET, the memory window widens (narrows) from 5.38 to 7.38 V (4.18 V), as the density of the positive (negative) trap charges increases. Moreover, we investigate the difference in the output drain current based on the interface trap charges during the memory operation.

Interface Trap Density of Gate-All-Around Silicon Nanowire Field-Effect Transistors With TiN Gate: Extraction and Compact Model

2013 ◽  
Vol 60 (8) ◽  
pp. 2457-2463 ◽  
Author(s):  
Faraz Najam ◽  
Yun Seop Yu ◽  
Keun Hwi Cho ◽  
Kyoung Hwan Yeo ◽  
Dong-Won Kim ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Silicon Nanowire ◽  
Trap Density ◽  
Compact Model ◽  
Interface Trap Density ◽  
Interface Trap

scholarly journals Interface Trap-Induced Temperature Dependent Hysteresis and Mobility in β-Ga2O3 Field-Effect Transistors

Nanomaterials ◽  
2021 ◽  
Vol 11 (2) ◽  
pp. 494
Author(s):  
Youngseo Park ◽  
Jiyeon Ma ◽  
Geonwook Yoo ◽  
Junseok Heo
Keyword(s):  
Gallium Oxide ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Gate Insulator ◽  
Interface Trap ◽  
Gate Bias ◽  
Temperature Dependent ◽  
Trap Charge ◽  
Time Constants ◽  
Channel Mobility

Interface traps between a gate insulator and beta-gallium oxide (β-Ga2O3) channel are extensively studied because of the interface trap charge-induced instability and hysteresis. In this work, their effects on mobility degradation at low temperature and hysteresis at high temperature are investigated by characterizing electrical properties of the device in a temperature range of 20–300 K. As acceptor-like traps at the interface are frozen below 230 K, the hysteresis becomes negligible but simultaneously the channel mobility significantly degrades because the inactive neutral traps allow additional collisions of electrons at the interface. This is confirmed by the fact that a gate bias adversely affects the channel mobility. An activation energy of such traps is estimated as 170 meV. The activated trap charges’ trapping and de-trapping processes in response to the gate pulse bias reveal that the time constants for the slow and fast processes decrease due to additionally activated traps as the temperature increases.

Vertical surround-gated silicon nanowire impact ionization field-effect transistors

2007 ◽  
Vol 90 (14) ◽  
pp. 142110 ◽  
Author(s):  
M. T. Björk ◽  
O. Hayden ◽  
H. Schmid ◽  
H. Riel ◽  
W. Riess
Keyword(s):  
Field Effect ◽  
Impact Ionization ◽  
Field Effect Transistors ◽  
Silicon Nanowire

scholarly journals Biologically sensitive field-effect transistors: from ISFETs to NanoFETs

2016 ◽  
Vol 60 (1) ◽  
pp. 81-90 ◽  
Author(s):  
Vivek Pachauri ◽  
Sven Ingebrandt
Keyword(s):  
Field Effect ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Field Effect Transistors ◽  
Silicon Nanowire ◽  
Label Free ◽  
Biomolecular Detection ◽  
New Device ◽  
Label Free Detection ◽  
History Of

Biologically sensitive field-effect transistors (BioFETs) are one of the most abundant classes of electronic sensors for biomolecular detection. Most of the time these sensors are realized as classical ion-sensitive field-effect transistors (ISFETs) having non-metallized gate dielectrics facing an electrolyte solution. In ISFETs, a semiconductor material is used as the active transducer element covered by a gate dielectric layer which is electronically sensitive to the (bio-)chemical changes that occur on its surface. This review will provide a brief overview of the history of ISFET biosensors with general operation concepts and sensing mechanisms. We also discuss silicon nanowire-based ISFETs (SiNW FETs) as the modern nanoscale version of classical ISFETs, as well as strategies to functionalize them with biologically sensitive layers. We include in our discussion other ISFET types based on nanomaterials such as carbon nanotubes, metal oxides and so on. The latest examples of highly sensitive label-free detection of deoxyribonucleic acid (DNA) molecules using SiNW FETs and single-cell recordings for drug screening and other applications of ISFETs will be highlighted. Finally, we suggest new device platforms and newly developed, miniaturized read-out tools with multichannel potentiometric and impedimetric measurement capabilities for future biomedical applications.

NAND And NOR Logic-In-Memory Comprising Silicon Nanowire Feedback Field-Effect Transistors

2021 ◽  
Author(s):  
Yejin Yang ◽  
Juhee Jeon ◽  
Jaemin Son ◽  
Kyoungah Cho ◽  
Sangsig Kim
Keyword(s):  
Processing Speed ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Silicon Nanowire ◽  
Logic Gate ◽  
High Energy ◽  
Zero Bias ◽  
Computing Systems ◽  
Data Movement

Abstract The processing of large amounts of data requires a high energy efficiency and fast processing time for high-performance computing systems. However, conventional von Neumann computing systems have performance limitations because of bottlenecks in data movement between separated processing and memory hierarchy, which causes latency and high power consumption. To overcome this hindrance, logic-in-memory (LIM) has been proposed that performs both data processing and memory operations. Here, we present a NAND and NOR LIM composed of silicon nanowidre feedback field-effect transistors, whose configuration resembles that of CMOS logic gate circuits. The LIM can perform memory operations to retain its output logic under zero-bias conditions as well as logic operations with a high processing speed of nanoseconds. The newly proposed dynamic voltage-transfer characteristics verify the operating principle of the LIM. This study demonstrates that the NAND and NOR LIM has promising potential to resolve power and processing speed issues.

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