Accurate modeling of the influence of back gate bias and interface roughness on the threshold voltage of nanoscale DG MOSFETs

2013 ◽  
Vol 53 (3) ◽  
pp. 363-370 ◽  
Author(s):  
Abhijit Biswas ◽  
Swagata Bhattacherjee
Keyword(s):  
Threshold Voltage ◽  
Interface Roughness ◽  
Gate Bias ◽  
Back Gate

New pixel circuits for controlling threshold voltage by back-gate bias voltage using crystalline oxide semiconductor FETs

2015 ◽  
Vol 24 (1) ◽  
pp. 35-43 ◽  
Author(s):  
Makoto Kaneyasu ◽  
Kouhei Toyotaka ◽  
Hideaki Shishido ◽  
Toshiyuki Isa ◽  
Shingo Eguchi ◽  
...  
Keyword(s):  
Bias Voltage ◽  
Threshold Voltage ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Back Gate ◽  
Crystalline Oxide

57.3:Distinguished Paper: New Pixel Circuits for Controlling Threshold Voltage by Back-gate Bias Voltage using Crystalline Oxide Semiconductor FETs

2015 ◽  
Vol 46 (1) ◽  
pp. 857-860 ◽  
Author(s):  
Makoto Kaneyasu ◽  
Kouhei Toyotaka ◽  
Hideaki Shishido ◽  
Toshiyuki Isa ◽  
Shingo Eguchi ◽  
...  
Keyword(s):  
Bias Voltage ◽  
Threshold Voltage ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Back Gate ◽  
Crystalline Oxide

Suppression of Timing Variations due to Random Dopant Fluctuation by Back-Gate Bias in a Nanometer CMOS Inverter

2020 ◽  
Vol 13 ◽  
Author(s):  
Kai Zhang ◽  
Weifeng Lü ◽  
Peng Si ◽  
Zhifeng Zhao ◽  
Tianyu Yu
Keyword(s):  
Monte Carlo ◽  
Integrated Circuits ◽  
Metal Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Cmos Inverter ◽  
Back Gate ◽  
Random Dopant Fluctuation ◽  
Random Dopant

Background: In state-of-the-art nanometer metal-oxide-semiconductor-field-effect- transistors (MOSFETs), optimization of timing characteristic is one of the major concerns in the design of modern digital integrated circuits. Objective: This study proposes an effective back-gate-biasing technique to comprehensively investigate the timing and its variation due to random dopant fluctuation (RDF) employing Monte Carlo methodology. Methods: To analyze RDF-induced timing variation in a 22-nm complementary metal-oxide semiconductor (CMOS) inverter, an ensemble of 1000 different samples of channel-doping for negative metal-oxide semiconductor (NMOS) and positive metal-oxide semiconductor (PMOS) was reproduced and the input/output curves were measured. Since back-gate bias is technology dependent, we present in parallel results with and without VBG. Results: It is found that the suppression of RDF-induced timing variations can be achieved by appropriately adopting back-gate voltage (VBG) through measurements and detailed Monte Carlo simulations. Consequently, the timing parameters and their variations are reduced and, moreover, that they are also insensitive to channel doping with back-gate bias. Conclusion: Circuit designers can appropriately use back-gate bias to minimize timing variations and improve the performance of CMOS integrated circuits.

Development of 1200 V, 3.7 mΩ-cm2 4H-SiC DMOSFETs for Advanced Power Applications

2012 ◽  
Vol 717-720 ◽  
pp. 1059-1064 ◽  
Author(s):  
Sei Hyung Ryu ◽  
Lin Cheng ◽  
Sarit Dhar ◽  
Craig Capell ◽  
Charlotte Jonas ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Room Temperature ◽  
Voltage Drop ◽  
Drain Current ◽  
Subthreshold Swing ◽  
Active Area ◽  
Gate Bias ◽  
Forward Voltage ◽  
Recent Developments ◽  
Forward Voltage Drop

We present our recent developments in 4H-SiC power DMOSFETs. 4H-SiC DMOSFETs with a room temperature specific on-resistance of 3.7 mΩ-cm2 with a gate bias of 20 V, and an avalanche voltage of 1550 V with gate shorted to source, was demonstrated. A threshold voltage of 3.5 V was extracted from the power DMOSFET, and a subthreshold swing of 200 mV/dec was measured. The device was successfully scaled to an active area of 0.4 cm2, and the resulting device showed a drain current of 377 A at a forward voltage drop of 3.8 V at 25oC.

Development of 8 mΩ-cm2, 1.8 kV 4H-SiC DMOSFETs

2006 ◽  
Vol 527-529 ◽  
pp. 1261-1264 ◽  
Author(s):  
Sei Hyung Ryu ◽  
Sumi Krishnaswami ◽  
Brett A. Hull ◽  
Bradley Heath ◽  
Mrinal K. Das ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Room Temperature ◽  
Elevated Temperatures ◽  
Gate Length ◽  
Gate Bias ◽  
Low Loss ◽  
Layer Resistance ◽  
Switching Characteristics ◽  
Mos Gate ◽  
Drift Layer

8 mΩ-cm2, 1.8 kV power DMOSFETs in 4H-SiC are presented in this paper. A 0.5 μm long MOS gate length was used to minimize the MOS channel resistance. The DMOSFETs were able to block 1.8 kV with the gate shorted to the source. At room temperature, a specific onresistance of 8 mΩ-cm2 was measured with a gate bias of 15 V. At 150 oC, the specific onresistance increased to 9.6 mΩ-cm2. The increase in drift layer resistance due to a decrease in bulk electron mobility was partly cancelled out by the negative shift in MOS threshold voltage at elevated temperatures. The device demonstrated extremely fast, low loss switching characteristics. A significant improvement in converter efficiency was observed when the 4H-SiC DMOSFET was used instead of an 800 V silicon superjunction MOSFET in a simple boost converter configuration.

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