scholarly journals Theory and experimental verification of configurable computing with stochastic memristors

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Rawan Naous ◽  
Anne Siemon ◽  
Michael Schulten ◽  
Hamzah Alahmadi ◽  
Andreas Kindsmüller ◽  
...  
Keyword(s):  
Performance Metrics ◽  
Supply Voltage ◽  
Logic Gates ◽  
Switching Behavior ◽  
Probabilistic Logic ◽  
Approximate Computing ◽  
Unconventional Computing ◽  
Configurable Computing ◽  
Theoretical Formulation ◽  
Computing Paradigm

AbstractThe inevitable variability within electronic devices causes strict constraints on operation, reliability and scalability of the circuit design. However, when a compromise arises among the different performance metrics, area, time and energy, variability then loosens the tight requirements and allows for further savings in an alternative design scope. To that end, unconventional computing approaches are revived in the form of approximate computing, particularly tuned for resource-constrained mobile computing. In this paper, a proof-of-concept of the approximate computing paradigm using memristors is demonstrated. Stochastic memristors are used as the main building block of probabilistic logic gates. As will be shown in this paper, the stochasticity of memristors’ switching characteristics is tightly bound to the supply voltage and hence to power consumption. By scaling of the supply voltage to appropriate levels stochasticity gets increased. In order to guide the design process of approximate circuits based on memristors a realistic device model needs to be elaborated with explicit emphasis of the probabilistic switching behavior. Theoretical formulation, probabilistic analysis, and simulation of the underlying logic circuits and operations are introduced. Moreover, the expected output behavior is verified with the experimental measurements of valence change memory cells. Hence, it is shown how the precision of the output is varied for the sake of the attainable gains at different levels of available design metrics. This approach represents the first proposition along with physical verification and mapping to real devices that combines stochastic memristors into unconventional computing approaches.

Power–Delay-Error-Efficient Approximate Adder for Error-Resilient Applications

2019 ◽  
Vol 28 (10) ◽  
pp. 1950171 ◽  
Author(s):  
Vinay Kumar ◽  
Ankit Singh ◽  
Shubham Upadhyay ◽  
Binod Kumar
Keyword(s):  
Image Processing ◽  
Power Consumption ◽  
Logic Gate ◽  
Logic Gates ◽  
Error Tolerance ◽  
Approximate Computing ◽  
Processing Application ◽  
Error Resilient ◽  
Delay Performance ◽  
Prime Concern

Power dissipation has been the prime concern for CMOS circuits. Approximate computing is a potential solution for addressing this concern as it reduces power consumption resulting in improved performance in terms of power–delay product (PDP). Decrease of power consumption in approximate computing is achieved by approximating the demand of accuracy as per the error tolerance of the system. This paper presents a new approach for designing approximate adder by introducing inexactness in the existing logic gate(s). Approximated logic gates provide flexibility in designing low power error-resilient systems depending on the error tolerance of the applications such as image processing and data mining. The proposed approximate adder (PAA) has higher accuracy than existing approximate adders with normalized mean error distance of 0.123 and 0.1256 for 16-bit and 32-bit adder, respectively, and lower PDP of 1.924E[Formula: see text]18[Formula: see text]J for 16-bit adder and 5.808E[Formula: see text]18[Formula: see text]J for 32-bit adder. The PAA also performs better than some of the recent approximate adders reported in literature in terms of layout area and delay. Performance of PAA has also been evaluated with an image processing application.

scholarly journals Accurate Sampling with Noisy Forces from Approximate Computing

Computation ◽  
2020 ◽  
Vol 8 (2) ◽  
pp. 39 ◽  
Author(s):  
Varadarajan Rengaraj ◽  
Michael Lass ◽  
Christian Plessl ◽  
Thomas D. Kühne
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Computer Simulations ◽  
High Efficiency ◽  
Type Equation ◽  
Low Power Consumption ◽  
Approximate Computing ◽  
Expectation Values ◽  
Computing Paradigm ◽  
Custom Hardware

In scientific computing, the acceleration of atomistic computer simulations by means of custom hardware is finding ever-growing application. A major limitation, however, is that the high efficiency in terms of performance and low power consumption entails the massive usage of low precision computing units. Here, based on the approximate computing paradigm, we present an algorithmic method to compensate for numerical inaccuracies due to low accuracy arithmetic operations rigorously, yet still obtaining exact expectation values using a properly modified Langevin-type equation.

A Review on Memristive Stateful Logic

2013 ◽  
Vol 791-793 ◽  
pp. 1845-1849
Author(s):  
Xu Dong Fang ◽  
Yu Hua Tang ◽  
Jun Jie Wu
Keyword(s):  
Computer Architecture ◽  
Design Methodology ◽  
Logic Gates ◽  
Working Mechanism ◽  
General Design ◽  
Computing Paradigm ◽  
Pros And Cons ◽  
Logic Operations ◽  
Conventional Computer

With the realization of physical memristors, using memristors to perform stateful logic operations has been demonstrated feasible. In such operations, memristors simultaneously serve as latches and logic gates, thus enabling the in-situ computing which may open a new computing paradigm for computer architecture. In this paper, we first analyze two types of typical memristive stateful logic gates to reveal the working mechanism of the stateful logic, and then review the recent researches on the memristive stateful logic, and finally discuss the pros and cons of the stateful logic. We reach the conclusion that the stateful logic promises a novel computing paradigm which may revolutionize the conventional computer architecture, while its development is currently subjected to the state drift problem and is constrained by the lack of a general design methodology and physically verification.

Research on Timing of on-Chip Power Supply Noise with Analysis of Scientific Data Materials

2013 ◽  
Vol 310 ◽  
pp. 494-497
Author(s):  
Xiao Guang Li
Keyword(s):  
Power Supply ◽  
Supply Voltage ◽  
Timing Analysis ◽  
Logic Gates ◽  
Scientific Data ◽  
New Method ◽  
Power Supply Noise ◽  
Supply Noise ◽  
On Chip

Aiming at the problems of the influence in power-supply variations on timing analysis, this paper presents a new method to assign a supply-dependent hold margin based on analysis of scientific data materials, which describe a method to accurately characterize logic gates for the sensitivity of delay on supply-voltage variations, and then the method use a commercial microcontroller as a design example. Experiment results shows that the new method with analysis of scientific materials can get a good performance, even under the existing noise.

scholarly journals Logic Gates and Ring Oscillators Based on Ambipolar Nanocrystalline-Silicon TFTs

2013 ◽  
Vol 2013 ◽  
pp. 1-7 ◽  
Author(s):  
Anand Subramaniam ◽  
Kurtis D. Cantley ◽  
Eric M. Vogel
Keyword(s):  
Supply Voltage ◽  
Logic Gate ◽  
Logic Gates ◽  
Nanocrystalline Silicon ◽  
Propagation Delay ◽  
Stable Operation ◽  
Device Performance ◽  
Ring Oscillators ◽  
Bias Stress ◽  
Stress Degradation

Nanocrystalline silicon (nc-Si) thin film transistors (TFTs) are well suited for circuit applications that require moderate device performance and low-temperature CMOS-compatible processing below 250°C. Basic logic gate circuits fabricated using ambipolar nc-Si TFTs alone are presented and shown to operate with correct outputs at frequencies of up to 100 kHz. Ring oscillators consisting of nc-Si TFT-based inverters are also shown to operate at above 20 kHz with a supply voltage of 5 V, corresponding to a propagation delay of <10 μs/stage. These are the fastest circuits formed out of nanocrystalline silicon TFTs to date. The effect of bias stress degradation of TFTs on oscillation frequency is also explored, and relatively stable operation is shown with supply voltages >5 V for several hours.

scholarly journals Energy Efficient GDI Based Full Adders For Computing Applications

2020 ◽  
Vol 4 (6) ◽  
pp. 5-9
Author(s):  
Bilal N Md ◽  
Bhaskara Rao K ◽  
Mohan Das S
Keyword(s):  
Energy Consumption ◽  
Power Consumption ◽  
Energy Efficient ◽  
Supply Voltage ◽  
Logic Gates ◽  
Full Adder ◽  
Low Power Consumption ◽  
Basic Logic ◽  
Power Delay Product ◽  
Full Swing

This This paper presents energy efficient GDI based 1-bit full adder cells with low power consumption and lesser delay with full swing modified basic logic gates to have reduced Power Delay Product (PDP). The various full adders are effectively realized by means of full swing OR, AND and XOR gates with the noteworthy enhancement in their performance. The simulations for the designed circuits performed in cadence virtuoso tool with 45-nm CMOS technologies at a supply voltage of 1 Volts. The proposed 1-bit adder cells are compared with various basic adders based on speed, power consumption and energy (PDP). The proposed adder schemes with full swing basic cells achieve significant savings in terms of delay and energy consumption and which are more than 41% and 32% respectively in comparison to conventional “C-CMOS” 1-bit full adder and other existing adders.

scholarly journals Neural-Network Based Modeling of I/O Buffer Predriver under Power/Ground Supply Voltage Variations

Sensors ◽  
2021 ◽  
Vol 21 (18) ◽  
pp. 6074
Author(s):  
Malek Souilem ◽  
Jai Narayan Tripathi ◽  
Rui Melicio ◽  
Wael Dghais ◽  
Hamdi Belgacem ◽  
...  
Keyword(s):  
Neural Network ◽  
Supply Voltage ◽  
Extraction Procedure ◽  
Electrical Circuit ◽  
Switching Behavior ◽  
Series Data ◽  
Circuit Switching ◽  
Model Structure ◽  
Large Signal ◽  
Nonlinear Switching

This paper presents a neural-network based nonlinear behavioral modelling of I/O buffer that accounts for timing distortion introduced by nonlinear switching behavior of the predriver electrical circuit under power and ground supply voltage (PGSV) variations. Model structure and I/O device characterization along with extraction procedure were described. The last stage of the I/O buffer is modelled as nonlinear current-voltage (I-V) and capacitance voltage (C-V) functions capturing the nonlinear dynamic impedances of the pull-up and pull-down transistors. The mathematical model structure of the predriver was derived from the analysis of the large-signal electrical circuit switching behavior. Accordingly, a generic and surrogate multilayer neural network (NN) structure was considered in this work. Timing series data which reflects the nonlinear switching behavior of the multistage predriver’s circuit PGSV variations, were used to train the NN model. The proposed model was implemented in the time-domain solver and validated against the reference transistor level (TL) model and the state-of-the-art input-output buffer information specification (IBIS) behavioral model under different scenarios. The analysis of jitter was performed using the eye diagrams plotted at different metrics values.

scholarly journals Design Space Exploration on High-Order QAM Demodulation Circuits: Algorithms, Arithmetic and Approximation Techniques

Electronics ◽  
2021 ◽  
Vol 11 (1) ◽  
pp. 39
Author(s):  
Ioannis Stratakos ◽  
Vasileios Leon ◽  
Giorgos Armeniakos ◽  
George Lentaris ◽  
Dimitrios Soudris
Keyword(s):  
Fixed Point ◽  
Orthogonal Frequency Division Multiplexing ◽  
Design Space Exploration ◽  
Performance Metrics ◽  
Circuit Complexity ◽  
Error Rates ◽  
High Order ◽  
Approximate Computing ◽  
Clock Frequency ◽  
Approximation Techniques

Every new generation of wireless communication standard aims to improve the overall performance and quality of service (QoS), compared to the previous generations. Increased data rates, numbers and capabilities of connected devices, new applications, and higher data volume transfers are some of the key parameters that are of interest. To satisfy these increased requirements, the synergy between wireless technologies and optical transport will dominate the 5G network topologies. This work focuses on a fundamental digital function in an orthogonal frequency-division multiplexing (OFDM) baseband transceiver architecture and aims at improving the throughput and circuit complexity of this function. Specifically, we consider the high-order QAM demodulation and apply approximation techniques to achieve our goals. We adopt approximate computing as a design strategy to exploit the error resiliency of the QAM function and deliver significant gains in terms of critical performance metrics. Particularly, we take into consideration and explore four demodulation algorithms and develop accurate floating- and fixed-point circuits in VHDL. In addition, we further explore the effects of introducing approximate arithmetic components. For our test case, we consider 64-QAM demodulators, and the results suggest that the most promising design provides bit error rates (BER) ranging from 10−1 to 10−4 for SNR 0–14 dB in terms of accuracy. Targeting a Xilinx Zynq Ultrascale+ ZCU106 (XCZU7EV) FPGA device, the approximate circuits achieve up to 98% reduction in LUT utilization, compared to the accurate floating-point model of the same algorithm, and up to a 122% increase in operating frequency. In terms of power consumption, our most efficient circuit configurations consume 0.6–1.1 W when operating at their maximum clock frequency. Our results show that if the objective is to achieve high accuracy in terms of BER, the prevailing solution is the approximate LLR algorithm configured with fixed-point arithmetic and 8-bit truncation, providing 81% decrease in LUTs and 13% increase in frequency and sustains a throughput of 323 Msamples/s.

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