scholarly journals Bottom-up water-based solution synthesis for a large MoS2 atomic layer for thin-film transistor applications

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Young-Jin Kwack ◽  
Thi Thu Thuy Can ◽  
Woon-Seop Choi
Keyword(s):  
Thin Film ◽  
Lattice Structure ◽  
Thin Film Transistor ◽  
Solution Process ◽  
Atomic Layer ◽  
Water Soluble ◽  
Solution Synthesis ◽  
Bottom Up ◽  
Water Based ◽  
One Step

A bottom-up water-based solution-process method was developed for atomic layered MoS2 with a one-step annealing process and no sulfurization. The chosen MoS2 precursor is water soluble and was carefully formulated to obtain good coating properties on a silicon substrate. The coated precursor was annealed in a furnace one time to crystallize it. This method can obtain a large and uniform atomic layer of 2D MoS2 with 2H lattice structure. The number of atomic layers (4–7) was controlled through the precursor concentrations and showed good uniformity, which was confirmed by STEM and AFM. Four types of thin-film transistors (TFTs) were prepared from the solution-processed MoS2 on Al2O3 and SiO2 dielectric with either thermal evaporated Al or printed Ag source and drain electrodes. The best result shows an improved mobility of 8.5 cm2 V−1 s−1 and a reasonable on–off ratio of about 1.0 × 105 with solid output saturation.

Effects of Drying Temperature on Surface Morphology and Electric Behavior of IGZO Thin Film Prepared by Solution Process

2015 ◽  
Vol 1731 ◽  
Author(s):  
Nobuko Fukuda ◽  
Shintaro Ogura ◽  
Koji Abe ◽  
Hirobumi Ushijima
Keyword(s):  
Thin Film ◽  
Organic Solvents ◽  
Room Temperature ◽  
Thin Film Transistor ◽  
Solution Process ◽  
Precursor Solution ◽  
Drying Process ◽  
Minor Variation ◽  
Drying Temperature ◽  
Metal Nitrates

ABSTRACTWe have achieved a drastic improvement of the performance as thin film transistor (TFT) for solution-processed IGZO thin film by controlling drying temperature of solvents containing the precursor solution. The IGZO-precursor solution was prepared by mixing of metal nitrates and two kinds of organic solvents, 2-methoxyethanol (2ME) and 2,2,2-trifluoroethanol (TFE). 2ME was used for dissolving metal nitrates. TFE was added as a solvent for reducing surface tension as small as possible, leading to improvement of the wettability of the precursor solution on the surface of the substrate. In order to discuss the relationship between morphology and drying process, the spin-coated IGZO-precursor films were dried at room temperature and 140 °C on a hotplate, respectively. Annealing of the both films was carried out at 300 °C in an electric oven for 60 min after each drying process. Drying at room temperature provides a discontinuous film, resulting in a large variation of the TFT performance. On the other hand, drying at 140 °C provides a continuous film, resulting in the higher TFT performance and a minor variation. The difference in surface morphologies would be derived from the evaporation rate of the organic solvents. The rapid evaporation at 140 °C brings about rapid pinning of the spin-coated precursor layer on the substrate. Preparation process via the drying at 140 °C gave ∼ 1 cm2 V-1 s-1 of the saturated mobility, quite small hysteresis, and 107∼ 108 of the on-off ratio.

scholarly journals Tuning the electrical performance and bias stability of a semiconducting SWCNT thin film transistor with an atomic layer deposited AlZrOx composite

RSC Advances ◽  
2017 ◽  
Vol 7 (83) ◽  
pp. 52517-52523 ◽  
Author(s):  
Jun Li ◽  
Chuan-Xin Huang ◽  
Jian-Hua Zhang
Keyword(s):  
Thin Film ◽  
Carbon Nanotube ◽  
Thin Film Transistors ◽  
Thin Film Transistor ◽  
Atomic Layer ◽  
Electrical Performance ◽  
Solution Processed ◽  
Single Walled Carbon Nanotube ◽  
Single Walled Carbon ◽  
Bias Stability

Solution-processed semiconducting single-walled carbon nanotube (s-SWCNT) thin film transistors (TFTs) based on different atomic layer deposited AlZrOx insulators are fabricated and characterized.

High-performance ZnO thin-film transistor fabricated by atomic layer deposition

2011 ◽  
Vol 26 (8) ◽  
pp. 085007 ◽  
Author(s):  
Byeong-Yun Oh ◽  
Young-Hwan Kim ◽  
Hee-Jun Lee ◽  
Byoung-Yong Kim ◽  
Hong-Gyu Park ◽  
...  
Keyword(s):  
Thin Film ◽  
Atomic Layer Deposition ◽  
High Performance ◽  
Thin Film Transistor ◽  
Atomic Layer ◽  
Zno Thin Film ◽  
Layer Deposition

Electrophoretic displays driven by all-oxide thin-film transistor backplanes fabricated using a solution process

2015 ◽  
Vol 212 (10) ◽  
pp. 2133-2140 ◽  
Author(s):  
Satoshi Inoue ◽  
Tue Trong Phan ◽  
Tomoko Hori ◽  
Hiroaki Koyama ◽  
Tatsuya Shimoda
Keyword(s):  
Thin Film ◽  
Thin Film Transistor ◽  
Solution Process ◽  
Oxide Thin Film

scholarly journals Voltage-Polarity Dependent Programming Behaviors of Amorphous In–Ga–Zn–O Thin-Film Transistor Memory with an Atomic-Layer-Deposited ZnO Charge Trapping Layer

2019 ◽  
Vol 14 (1) ◽  
Author(s):  
Dan-Dan Liu ◽  
Wen-Jun Liu ◽  
Jun-Xiang Pei ◽  
Lin-Yan Xie ◽  
Jingyong Huo ◽  
...  
Keyword(s):  
Thin Film ◽  
Oxygen Vacancy ◽  
Gate Voltage ◽  
Oxygen Vacancies ◽  
Thin Film Transistor ◽  
Charge Trapping ◽  
Atomic Layer ◽  
Gate Bias ◽  
Voltage Polarity ◽  
Bias Pulse

AbstractAmorphous In–Ga–Zn-O (a-IGZO) thin-film transistor (TFT) memories are attracting many interests for future system-on-panel applications; however, they usually exhibit a poor erasing efficiency. In this article, we investigate voltage-polarity-dependent programming behaviors of an a-IGZO TFT memory with an atomic-layer-deposited ZnO charge trapping layer (CTL). The pristine devices demonstrate electrically programmable characteristics not only under positive gate biases but also under negative gate biases. In particular, the latter can generate a much higher programming efficiency than the former. Upon applying a gate bias pulse of +13 V/1 μs, the device shows a threshold voltage shift (ΔVth) of 2 V; and the ΔVth is as large as −6.5 V for a gate bias pulse of −13 V/1 μs. In the case of 12 V/1 ms programming (P) and −12 V/10 μs erasing (E), a memory window as large as 7.2 V can be achieved at 103 of P/E cycles. By comparing the ZnO CTLs annealed in O2 or N2 with the as-deposited one, it is concluded that the oxygen vacancy (VO)-related defects dominate the bipolar programming characteristics of the TFT memory devices. For programming at positive gate voltage, electrons are injected from the IGZO channel into the ZnO layer and preferentially trapped at deep levels of singly ionized oxygen vacancy (VO+) and doubly ionized oxygen vacancy (VO2+). Regarding programming at negative gate voltage, electrons are de-trapped easily from neutral oxygen vacancies because of shallow donors and tunnel back to the channel. This thus leads to highly efficient erasing by the formation of additional ionized oxygen vacancies with positive charges.

scholarly journals Atomic Layer Deposition ZnO:N Thin Film Transistor: The Effects of N Concentration on the Device Properties

2010 ◽  
Vol 157 (2) ◽  
pp. H214 ◽  
Author(s):  
S. J. Lim ◽  
Jae-Min Kim ◽  
Doyoung Kim ◽  
Soonju Kwon ◽  
Jin-Seong Park ◽  
...  
Keyword(s):  
Thin Film ◽  
Atomic Layer Deposition ◽  
Thin Film Transistor ◽  
Atomic Layer ◽  
N Concentration ◽  
Layer Deposition ◽  
Device Properties

Threshold voltage control of a thin-film transistor using an Al–Zn–O channel prepared using atomic layer deposition by controlling the Al dopant positions

RSC Advances ◽  
2016 ◽  
Vol 6 (95) ◽  
pp. 92534-92540 ◽  
Author(s):  
Eom-Ji Kim ◽  
Won-Ho Lee ◽  
Sung-Min Yoon
Keyword(s):  
Thin Film ◽  
Atomic Layer Deposition ◽  
Threshold Voltage ◽  
Thin Film Transistor ◽  
Voltage Control ◽  
Atomic Layer ◽  
Layer Deposition ◽  
Doped Zno ◽  
Active Channel

We proposed a methodology for controlling the threshold voltage by adjusting the position of the Al dopant layer within an Al-doped-ZnO active channel of a thin film transistor.

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