A simulation study to quantify the advantages of silicon-on-insulator (SOI) technology for low power

2001 ◽  
Author(s):  
D. Donaghy
Keyword(s):  
Low Power ◽  
Simulation Study ◽  
Silicon On Insulator ◽  
Soi Technology

scholarly journals Linearization Technique of Low Power Opamps in CMOS FD-SOI Technologies

Electronics ◽  
2021 ◽  
Vol 10 (15) ◽  
pp. 1800
Author(s):  
Wieslaw Kuzmicz
Keyword(s):  
Low Power ◽  
Negative Feedback ◽  
Silicon On Insulator ◽  
Operational Amplifiers ◽  
Back Gate ◽  
Fully Depleted ◽  
Linearization Technique ◽  
Mos Devices ◽  
Soi Technology

Negative feedback applied to the back gate of MOS devices available in FD-SOI (fully depleted silicon on insulator) CMOS technologies can be used to improve the linearity of operational amplifiers. Two operational amplifiers designed and fabricated in a 22 nm FD-SOI technology illustrate this technique, as well as its advantages and limitations.

Application of FIB Circuit Edit in Analysis of Memory Failure of SOI Devices

2006 ◽  
Author(s):  
Z. G. Song ◽  
S. K. Loh ◽  
X. H. Zheng ◽  
S.P. Neo ◽  
C. K. Oh
Keyword(s):  
Focused Ion Beam ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Silicon On Insulator ◽  
First Case ◽  
Edx Analyses ◽  
Memory Failure ◽  
Soi Devices ◽  
Voltage Contrast ◽  
Soi Technology

Abstract This article presents two cases to demonstrate the application of focused ion beam (FIB) circuit edit in analysis of memory failure of silicon on insulator (SOI) devices using XTEM and EDX analyses. The first case was a single bit failure of SRAM units manufactured with 90 nm technology in SOI wafer. The second case was the whole column failure with a single bit pass for a SRAM unit. From the results, it was concluded that FIB circuit edit and electrical characterization is a good methodology for further narrowing down the defective location of memory failure, especially for SOI technology, where contact-level passive voltage contrast is not suitable.

LOW-NOISE SILICON-ON-INSULATOR HALL DEVICES

2004 ◽  
Vol 04 (02) ◽  
pp. L345-L354 ◽  
Author(s):  
Y. HADDAB ◽  
V. MOSSER ◽  
M. LYSOWEC ◽  
J. SUSKI ◽  
L. DEMEUS ◽  
...  
Keyword(s):  
Noise Level ◽  
Low Voltage ◽  
Silicon Layer ◽  
Electrical Current ◽  
Low Noise ◽  
Silicon On Insulator ◽  
Technological Parameters ◽  
Wide Range ◽  
Hall Sensors ◽  
Soi Technology

Hall sensors are used in a very wide range of applications. A very demanding one is electrical current measurement for metering purposes. In addition to high precision and stability, a sufficiently low noise level is required. Cost reduction through sensor integration with low-voltage/low-power electronics is also desirable. The purpose of this work is to investigate the possible use of SOI (Silicon On Insulator) technology for this integration. We have fabricated SOI Hall devices exploring the useful range of silicon layer thickness and doping level. We show that noise is influenced by the presence of LOCOS and p-n depletion zones near the edges of the active zones of the devices. A proper choice of SOI technological parameters and process flow leads to up to 18 dB reduction in Hall sensor noise level. This result can be extended to many categories of devices fabricated using SOI technology.

STUDY OF ELECTRICAL CHARACTERISTIC FOR 50NM AND 10NM SOI BODY THICKNESS IN MOSFET DEVICE

2015 ◽  
Vol 77 (21) ◽  
Author(s):  
M.N.I.A Aziz ◽  
F. Salehuddin ◽  
A.S.M. Zain ◽  
K.E. Kaharudin
Keyword(s):  
Thin Film ◽  
Electrical Characteristic ◽  
Silicon On Insulator ◽  
Electrical Characteristics ◽  
Short Channel ◽  
Doping Density ◽  
Soi Mosfet ◽  
Buried Oxide ◽  
Soi Technology ◽  
Better Than

Silicon-on-insulator (SOI) technology is an effective approach of mitigating the short channel effect (SCE) problems. The SOI is believed to be capable of suppressing the SCE, thereby improving the overall electrical characteristics of MOSFET device. SCE in SOI MOSFET is heavily influenced by thin film thickness, thin-film doping density and buried oxide (BOX) thickness. This paper will analyze the effect of BOX towards SOI MOSFET device. The 50nm and 10nm thickness of buried oxide in SOI MOSFET was developed by using SILVACO TCAD tools, specifically known as Athena and Atlas modules. From the observation, the electrical characteristic of 100nm thickness is slightly better than 50nm and 10nm. It is observed that the value drive current of 10nm and 100nm thickness SOI MOSFET was 6.9% and 11% lower than 50nm respectively, but the overall 50nm is superior. However, the electrical characteristics of 10nm SOI MOSFET are still closer and within the range of ITRS 2013 prediction.

Simulation study of a novel 3D SPAD pixel in an advanced FD-SOI technology

2017 ◽  
Vol 128 ◽  
pp. 163-171 ◽  
Author(s):  
M.M. Vignetti ◽  
F. Calmon ◽  
P. Lesieur ◽  
A. Savoy-Navarro
Keyword(s):  
Simulation Study ◽  
Soi Technology

Recent Progress in SOI Materials and Devices for VLSI Applications

1993 ◽  
Vol 316 ◽  
Author(s):  
H. H. Hosack
Keyword(s):  
High Performance ◽  
Large Scale ◽  
Recent Progress ◽  
Low Voltage ◽  
Silicon On Insulator ◽  
Significant Interest ◽  
Significant Performance ◽  
Cmos Ic ◽  
Bulk Processing ◽  
Soi Technology

Silicon-On-Insulator (SOI) technology [1-4] has been shown to have significant performance and fabrication advantages over conventional bulk processing for a wide variety of large scale CMOS IC applications. Advantages in radiation environments has generated significant interest in this technology from military and space science communities [5,6]. Possible advantages of SOI technology for low power, low voltage and high performance circuit applications is under serious consideration by several commercial IC manufacturers [7,8].

scholarly journals Linearization Technique of Low Power Opamps in CMOS FD-SOI Technologies

2021 ◽  
Author(s):  
Wieslaw Kuzmicz
Keyword(s):  
Low Power ◽  
Negative Feedback ◽  
Operational Amplifiers ◽  
Back Gate ◽  
Linearization Technique ◽  
Mos Devices ◽  
Soi Technology

Negative feedback to the back gate of MOS devices available in FD-SOI technologies can be used to improve linearity of operational amplifiers. Two operational amplifiers designed and fabricated in a 22nm FD-SOI technology illustrate this technique, its advantages and limitations.

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