Design and analysis of high performance current reference generators for low-power CMOS data converters

1999 ◽  
Vol 46 (5) ◽  
pp. 647-652 ◽  
Author(s):  
Jin-Sheng Wang ◽  
Chin-Long Wey
Keyword(s):  
Low Power ◽  
High Performance ◽  
Data Converters ◽  
Current Reference ◽  
Low Power Cmos

scholarly journals A HIGH-PERFORMANCE AND LOW-POWER DELAY BUFFER

2013 ◽  
pp. 78-82
Author(s):  
GOPALA KRISHNA.M ◽  
UMA SANKAR.CH ◽  
NEELIMA. S ◽  
KOTESWARA RAO.P
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Flip Flop ◽  
Ring Counter ◽  
Double Edge ◽  
Low Power Cmos ◽  
Cmos Vlsi

In this paper, presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Speed-Power product is reduced by 56%-63% compared to other double edge triggered flip-flops. This design is suitable for high-speed, low-power CMOS VLSI design applications.

A Low-Power CMOS Current Reference for Piezoelectric Energy Harvesters

2020 ◽  
Vol 67 (8) ◽  
pp. 3403-3410
Author(s):  
Rui Carvalho ◽  
Tao Dong ◽  
Zhaochu Yang ◽  
Haakon Karlsen ◽  
Luis Goncalves ◽  
...  
Keyword(s):  
Low Power ◽  
Energy Harvesters ◽  
Current Reference ◽  
Piezoelectric Energy ◽  
Low Power Cmos

Design of Low Power CMOS Comparator using 180nm Technology for ADC Application

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 11-13
Author(s):  
Truptimayee Behera ◽  
Ritisnigdha Das
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Input Voltage ◽  
Clock Frequency ◽  
Nmos Transistor ◽  
Body Effect ◽  
Low Power Dissipation ◽  
Low Power Cmos

In our design of CMOS comparator with high performance using GPDK 180nm technology we optimize these parameters. We analyse the transient response of the schematic design and the gain is calculated in AC analysis and also we measure the power dissipation. The circuit is built by using PMOS and NMOS transistor with a body effect. A plot of phase and gain also discussed in the paper. Finally a test schematic is built and transient analysis for an input voltage of 2V is measured using Cadence virtuoso. Simulation results are presented and it shows that this design can work under high speed clock frequency 200MHz. The design has low power dissipation.

A Low Power, Precision SAR Analog to Digital Converter for High Temperature Applications

2014 ◽  
Vol 2014 (HITEC) ◽  
pp. 000053-000057
Author(s):  
Jeff Watson ◽  
Maithil Pachchigar
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
High Performance ◽  
High Reliability ◽  
Data Converters ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Data Converter ◽  
Precision Data ◽  
Analog To Digital

A growing number of industries are calling for low power electronics that operate reliably at temperatures of 175°C and higher. Many of these applications require a precision data acquisition signal chain in order to digitize analog data so that it can be collected and processed. Designing circuits that meet these needs can be very challenging, requiring a data converter that can deliver high performance and reliability in these harsh environments. There are currently a very limited number of integrated circuits commercially available that are specified for operation at these temperatures, and no low power precision data converters with sample rates greater than 100kSPS. This paper presents a new 210°C rated precision analog to digital converter capable of sample rates up to 600 kSPS with 16 bit resolution while maintaining low power consumption and packaged in a small form factor. We will explore the converter architecture of this ADC, present initial test results, and show how high reliability is achieved through qualification and advanced packaging techniques.

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