Influence of the Threshold Voltage Hysteresis and the Drain Induced Barrier Lowering on the Dynamic Transfer Characteristic of SiC Power MOSFETs

Author(s):  
Patrick Hofstetter ◽  
Robert W. Maier ◽  
Mark-M. Bakran
2008 ◽  
Vol 600-603 ◽  
pp. 895-900 ◽  
Author(s):  
Anant K. Agarwal ◽  
Albert A. Burk ◽  
Robert Callanan ◽  
Craig Capell ◽  
Mrinal K. Das ◽  
...  

In this paper, we review the state of the art of SiC switches and the technical issues which remain. Specifically, we will review the progress and remaining challenges associated with SiC power MOSFETs and BJTs. The most difficult issue when fabricating MOSFETs has been an excessive variation in threshold voltage from batch to batch. This difficulty arises due to the fact that the threshold voltage is determined by the difference between two large numbers, namely, a large fixed oxide charge and a large negative charge in the interface traps. There may also be some significant charge captured in the bulk traps in SiC and SiO2. The effect of recombination-induced stacking faults (SFs) on majority carrier mobility has been confirmed with 10 kV Merged PN Schottky (MPS) diodes and MOSFETs. The same SFs have been found to be responsible for degradation of BJTs.


2019 ◽  
Vol 963 ◽  
pp. 738-741
Author(s):  
Hiroshi Kono ◽  
Teruyuki Ohashi ◽  
Takao Noda ◽  
Kenya Sano

Neutron single event effect (SEE) tolerance of SiC power MOSFETs with different drift region design were evaluated. The SEE is detected over the SEE threshold voltage (VSEE). The failure rate increases exponentially as the drain voltage increases above VSEE. The device with higher avalanche breakdown voltage has higher SEE threshold voltage. The neutron SEE tolerance of MOSFETs and PiN diodes of the same epitaxial structure were also evaluated. There was no significant difference in the neutron SEE tolerance of these devices.


Author(s):  
Susanna Yu ◽  
Tianshi Liu ◽  
Shengnan Zhu ◽  
Diang Xing ◽  
Arash Salemi ◽  
...  

Energies ◽  
2021 ◽  
Vol 14 (24) ◽  
pp. 8283
Author(s):  
Hema Lata Rao Maddi ◽  
Susanna Yu ◽  
Shengnan Zhu ◽  
Tianshi Liu ◽  
Limeng Shi ◽  
...  

This article provides a detailed study of performance and reliability issues and trade-offs in silicon carbide (SiC) power MOSFETs. The reliability issues such as threshold voltage variation across devices from the same vendor, instability of threshold voltage under positive and negative gate bias, long-term reliability of gate oxide, screening of devices with extrinsic defects by means of gate voltage, body diode degradation, and short circuit withstand time are investigated through testing of commercial devices from different vendors and two-dimensional simulations. Price roadmap and foundry models of SiC MOSFETs are discussed. Future development of mixed-mode CMOS circuits with high voltage lateral MOSFETs along with 4−6× higher power handling capability compared to silicon circuits has been described.


2013 ◽  
Vol 2013 (HITEN) ◽  
pp. 000275-000280 ◽  
Author(s):  
R. J. Kaplar ◽  
D. R. Hughart ◽  
S. Atcitty ◽  
J. D. Flicker ◽  
S. DasGupta ◽  
...  

Commercially available, 1200 V SiC power MOSFETs have been characterized under bias-temperature stress conditions. Two generations of devices from a single manufacturer were tested. For the first-generation MOSFETs, both plastic- and metal-packaged devices were evaluated, whereas for the second-generation MOSFETs, only plastic-packaged devices were tested. Threshold voltage was observed to decrease with increasing temperature in the absence of gate bias stress, as expected. Drain leakage current increased with increasing temperature above the rated temperature of 125°C for first-generation plastic-packaged parts, with the leakage ~10× higher for the plastic-packaged parts compared to the metal-packaged parts. A negative gate voltage was shown to reduce drain leakage current for the metal-packaged parts only, suggesting a parasitic leakage path associated with the plastic packaging. The threshold voltage shift ΔVT was minimal for T < 125°C. ΔVT increased with increasing temperature above 125°C, and was larger for negative gate voltage bias stress, suggesting that the oxide is more sensitive to trapping of holes than trapping of electrons. ΔVT was insensitive to the type of package. The second-generation SiC MOSFET showed significantly less susceptibility to bias temperature stress, especially for negative gate voltage, indicating improvement in device design and/or processing in the second-generation MOSFET. Switching gate stress showed complex behavior, with a rapid initial shift in VT followed by a much slower shift. Initial testing indicates a strong dependence on duty cycle and possible influence of self-heating. More detailed study of reliability under switching conditions is needed.


2020 ◽  
Vol 1004 ◽  
pp. 671-679 ◽  
Author(s):  
Salvatore Cascino ◽  
Mario Saggio ◽  
Alfio Guarnera

In this paper, we report on the simulation results of instability threshold voltage of SiC MOSFET device. Hysteresis cycles of threshold voltage suggest that trapping and detrapping phenomena of electrons from the SiC layer into the oxide traps occur. Experiment suggests that positive threshold voltage shifts (ΔVth) caused by a positive stress voltage to the gate, are almost fully recovered by applying negative stress voltage. This work assumes uniform trap densities extending from SiC interface at a limited depth into oxide.


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