Integrated silicon optical switch for high-speed network-on-chip

2020 ◽  
Author(s):  
Ho Duc Tam Linh ◽  
Nguyen Van Quang ◽  
Dao Duy Tu ◽  
Nguyen Van An ◽  
Vuong Quang Phuoc
Keyword(s):  
High Speed ◽  
Optical Switch ◽  
Network On Chip ◽  
High Speed Network ◽  
On Chip

INFLUENCE OF TRAFFIC CORRELATION ON THE PERFORMANCE OF NETWORK-ON-CHIP DESIGNS

2010 ◽  
Vol 19 (03) ◽  
pp. 655-669 ◽  
Author(s):  
FANG WANG
Keyword(s):  
High Speed ◽  
Communication Complexity ◽  
Network On Chip ◽  
Strong Correlations ◽  
Communication Performance ◽  
Seamless Integration ◽  
High Speed Network ◽  
On Chip ◽  
Point To Point ◽  
The Impact

Advance in semiconductor technologies enables seamless integration of hundreds of cores on a single silicon die, which requires high communication performance. To deal with the increasing communication complexity of System-on-Chip (SoC), Network-on-Chip (NoC) has been recently proposed as an alternative to the conventional point-to-point links and bus based communication fabrics. In practice, to facilitate NoC design evaluation and optimization, Poisson traffic or Bernoulli traffic models are generally assumed. However, actual measurements showed that real high speed network traffic always has strong correlations. The objective of this paper is to investigate the impact of traffic correlations on the performance of NoC design. Experimental results show that traffic correlation degrades the performance of NoC design and unrealistic traffic assumptions may yield unacceptable designs.

scholarly journals Six-port optical switch for cluster-mesh photonic network-on-chip

Nanophotonics ◽  
2018 ◽  
Vol 7 (5) ◽  
pp. 827-835 ◽  
Author(s):  
Hao Jia ◽  
Ting Zhou ◽  
Yunchou Zhao ◽  
Yuhao Xia ◽  
Jincheng Dai ◽  
...  
Keyword(s):  
High Performance ◽  
Optical Switching ◽  
Optical Switch ◽  
Optical Signal ◽  
Network On Chip ◽  
Transmission Experiment ◽  
Photonic Network ◽  
Benes Network ◽  
On Chip ◽  
Spectral Responses

AbstractPhotonic network-on-chip for high-performance multi-core processors has attracted substantial interest in recent years as it offers a systematic method to meet the demand of large bandwidth, low latency and low power dissipation. In this paper we demonstrate a non-blocking six-port optical switch for cluster-mesh photonic network-on-chip. The architecture is constructed by substituting three optical switching units of typical Spanke-Benes network to optical waveguide crossings. Compared with Spanke-Benes network, the number of optical switching units is reduced by 20%, while the connectivity of routing path is maintained. By this way the footprint and power consumption can be reduced at the expense of sacrificing the network latency performance in some cases. The device is realized by 12 thermally tuned silicon Mach-Zehnder optical switching units. Its theoretical spectral responses are evaluated by establishing a numerical model. The experimental spectral responses are also characterized, which indicates that the optical signal-to-noise ratios of the optical switch are larger than 13.5 dB in the wavelength range from 1525 nm to 1565 nm. Data transmission experiment with the data rate of 32 Gbps is implemented for each optical link.

Network-on-Chip for Low Power MAP Decoder Using Folded Technique and CORDIC Algorithm for 5G Network

2021 ◽  
pp. 96-108
Author(s):  
Shiyamala S. ◽  
Vijay Soorya J. ◽  
Sanjay P. S. ◽  
Sathappan K.
Keyword(s):  
Turbo Codes ◽  
High Speed ◽  
Life Time ◽  
Full Adder ◽  
Network On Chip ◽  
Cordic Algorithm ◽  
Effective Manner ◽  
Constraint Length ◽  
On Chip ◽  
Map Decoder

With different constraint length (K), time scale, and code rate, modified MAP (maximum a posteriori) decoder architecture using folding technique, which has a linear life time chart, is developed, and dedicated turbo codes will be placed in a network-on-chip for various wireless applications. Folded techniques mitigated the number of latches used in interleaving and deinterleaving unit by adopting forward and backward resource utilizing method to M-2, where M is the number of rows and end-to-end delay get reduced to 2M. By replacing conventional full adder by high speed adder using 2 x 1 multiplexer to calculate the forward state metrics and reverse state metrics will minimize the power consumption utilization in an effective manner. In s similar way, CORDIC (Coordinated ROtation DIgital Computer) algorithm is used to calculate the LLR value and confer a highly precise value with less computational complexity by means of only shifting and adding methods.

Dual Monitoring Communication for Self-Aware Network-on-Chip

2012 ◽  
Vol 3 (3) ◽  
pp. 72-91
Author(s):  
Liang Guang ◽  
Ethiopia Nigussie ◽  
Juha Plosila ◽  
Hannu Tenhunen
Keyword(s):  
High Speed ◽  
Data Communication ◽  
Cmos Technology ◽  
Network On Chip ◽  
Time Profile ◽  
Self Awareness ◽  
Monitoring Networks ◽  
Communication Architecture ◽  
Run Time ◽  
On Chip

Self-aware and adaptive Network-on-Chip (NoC) with dual monitoring networks is presented. Proper monitoring interface is an essential prerequisite to adaptive system reconfiguration in parallel on-chip computing. This work proposes a DMC (dual monitoring communication) architecture to support self-awareness on the NoC platform. One type of monitoring communication is integrated with data channel, in order to trace the run-time profile of data communication in high-speed on-chip networking. The other type is separate from the data communication, and is needed to report the run-time profile to the supervising monitor. Direct latency monitoring on mesochronous NoC is presented as a case study and is directly traced in the integrated communication with a novel latency monitoring table in each router. The latency information is reported by the separate monitoring communication to the supervising monitor, which reconfigures the system to adjust the latency, for instance by dynamic voltage and frequency scaling. With quantitative evaluation using synthetic traces and real applications, the effectiveness and efficiency of direct latency monitoring with DMC architecture is demonstrated. The area overhead of DMC architecture is estimated to be small in 65nm CMOS technology.

scholarly journals Congestion-aware wireless network-on-chip for high-speed communication

Automatika ◽  
2019 ◽  
Vol 61 (1) ◽  
pp. 92-98
Author(s):  
M. Devanathan ◽  
V. Ranganathan ◽  
P. Sivakumar
Keyword(s):  
Wireless Network ◽  
High Speed ◽  
Network On Chip ◽  
On Chip ◽  
Congestion Aware

High Speed Low Power Ping Pong Buffering Based Network Interface for Network on Chip

2013 ◽  
Vol 9 (3) ◽  
pp. 322-331 ◽  
Author(s):  
K. Swaminathan ◽  
G. Lakshminarayanan ◽  
Seok-Bum Ko
Keyword(s):  
Low Power ◽  
High Speed ◽  
Network On Chip ◽  
Network Interface ◽  
Ping Pong ◽  
On Chip

scholarly journals Lightweight Cryptography for Network-on-Chip Data Encryption

2021 ◽  
Vol 2021 ◽  
pp. 1-10
Author(s):  
Riadh Ayachi ◽  
Ayoub Mhaouch ◽  
Abdessalem Ben Abdelali
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Network Performance ◽  
High Reliability ◽  
Data Encryption ◽  
Network On Chip ◽  
Security Problem ◽  
Finite State ◽  
On Chip ◽  
Main Component

System-on-chip (SoC) is the main processor for most recent applications such as the Internet of things (IoT). SoCs are composed of multiple blocks that communicate with each other through an integrated router. Data routing from a block to another poses many challenges. The network-on-chip (NoC) was used for the transmission of data from a source to a destination with high reliability, high speed, low power consumption, and low hardware occupation. An NoC is composed of a router, network links (NL), and network interface (NI). The main component of the NoC, the NI, is composed of an input/output FIFO, a finite state machine (FSM), pack, and depack modules. Data transmission from a block to another poses a security problem such as secret information extraction. In this paper, we proposed a data encryption framework for NoC based on a light encryption device (LED) algorithm. The main advantages of the proposed algorithm are to reduce the implementation area and to achieve high speed while reducing the power consumption. The proposed encryption framework was simulated Verilog/VHDL on the Xilinx ISE and implemented on the Xilinx Virtex 5 XC5VFX200T. The obtained results have shown that the proposed framework has a smaller area and higher speed compared to existing works. The proposed algorithm has reduced the NI implementation area and enhanced the network performance in terms of speed and security.

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