Electrical performance improvements on RFICs using bump chip carrier packages as compared to standard small outline packages

2002 ◽  
Author(s):  
T.S. Horng ◽  
S.M. Wu ◽  
J.Y. Li ◽  
C.T. Chiu ◽  
C.P. Hung
Keyword(s):  
Electrical Performance ◽  
Performance Improvements ◽  
Chip Carrier

Metal Microstructures in Advanced CMOS Devices

1996 ◽  
Vol 54 ◽  
pp. 358-359
Author(s):  
L. M. Gignac ◽  
K. P. Rodbell
Keyword(s):  
Grain Boundaries ◽  
Semiconductor Device ◽  
Chemical Vapor ◽  
Microstructural Characterization ◽  
Metal Films ◽  
Thin Metal ◽  
Electrical Performance ◽  
Thin Metal Films ◽  
Chemical Vapor Deposited ◽  
Boundary Properties

As advanced semiconductor device features shrink, grain boundaries and interfaces become increasingly more important to the properties of thin metal films. With film thicknesses decreasing to the range of 10 nm and the corresponding features also decreasing to sub-micrometer sizes, interface and grain boundary properties become dominant. In this regime the details of the surfaces and grain boundaries dictate the interactions between film layers and the subsequent electrical properties. Therefore it is necessary to accurately characterize these materials on the proper length scale in order to first understand and then to improve the device effectiveness. In this talk we will examine the importance of microstructural characterization of thin metal films used in semiconductor devices and show how microstructure can influence the electrical performance. Specifically, we will review Co and Ti silicides for silicon contact and gate conductor applications, Ti/TiN liner films used for adhesion and diffusion barriers in chemical vapor deposited (CVD) tungsten vertical wiring (vias) and Ti/AlCu/Ti-TiN films used as planar interconnect metal lines.

Effective performance improvement of organic thin film transistors with multi-layer modifications

2020 ◽  
Vol 91 (3) ◽  
pp. 30201
Author(s):  
Hang Yu ◽  
Jianlin Zhou ◽  
Yuanyuan Hao ◽  
Yao Ni
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Performance Enhancement ◽  
Organic Thin Film Transistors ◽  
Electrical Performance ◽  
Hole Injection ◽  
Organic Thin Film ◽  
Effective Performance ◽  
Significant Performance ◽  
P Type

Organic thin film transistors (OTFTs) based on dioctylbenzothienobenzothiophene (C8BTBT) and copper (Cu) electrodes were fabricated. For improving the electrical performance of the original devices, the different modifications were attempted to insert in three different positions including semiconductor/electrode interface, semiconductor bulk inside and semiconductor/insulator interface. In detail, 4,4′,4′′-tris[3-methylpheny(phenyl)amino] triphenylamine (m-MTDATA) was applied between C8BTBTand Cu electrodes as hole injection layer (HIL). Moreover, the fluorinated copper phthalo-cyanine (F16CuPc) was inserted in C8BTBT/SiO2 interface to form F16CuPc/C8BTBT heterojunction or C8BTBT bulk to form C8BTBT/F16CuPc/C8BTBT sandwich configuration. Our experiment shows that, the sandwich structured OTFTs have a significant performance enhancement when appropriate thickness modification is chosen, comparing with original C8BTBT devices. Then, even the low work function metal Cu was applied, a normal p-type operate-mode C8BTBT-OTFT with mobility as high as 2.56 cm2/Vs has been fabricated.

Degradation and SILC Effects of RPECVD sub-2.0nm Oxide/Nitride and Oxynitride Dielectrics Under Constant Current Stress

2002 ◽  
Vol 716 ◽  
Author(s):  
Yi-Mu Lee ◽  
Yider Wu ◽  
Joon Goo Hong ◽  
Gerald Lucovsky
Keyword(s):  
Leakage Current ◽  
Electrical Performance ◽  
Constant Current ◽  
Continuous Increase ◽  
Current Stress ◽  
Thermal Oxide ◽  
Stress Induced Leakage Current ◽  
Boron Penetration ◽  
Soft Breakdown ◽  
Induced Defects

AbstractConstant current stress (CCS) has been used to investigate the Stress-Induced Leakage Current (SILC) to clarify the influence of boron penetration and nitrogen incorporation on the breakdown of p-channel devices with sub-2.0 nm Oxide/Nitride (O/N) and oxynitride dielectrics prepared by remote plasma enhanced CVD (RPECVD). Degradation of MOSFET characteristics correlated with soft breakdown (SBD) and hard breakdown (HBD), and attributed to the increased gate leakage current are studied. Gate voltages were gradually decreased during SBD, and a continuous increase in SILC at low gate voltages between each stress interval, is shown to be due to the generation of positive traps which are enhanced by boron penetration. Compared to thermal oxides, stacked O/N and oxynitride dielectrics with interface nitridation show reduced SILC due to the suppression of boron penetration and associated positive trap generation. Devices stressed under substrate injection show harder breakdown and more severe degradation, implying a greater amount of the stress-induced defects at SiO2/substrate interface. Stacked O/N and oxynitride devices also show less degradation in electrical performance compared to thermal oxide devices due to an improved Si/SiO2 interface, and reduced gate-to-drain overlap region.

Correlation Between the Tunnelling Oxide and I-V Curves of MIS Photodiodes

2003 ◽  
Vol 762 ◽  
Author(s):  
H. Águas ◽  
L. Pereira ◽  
A. Goullet ◽  
R. Silva ◽  
E. Fortunato ◽  
...  
Keyword(s):  
Hydrogen Peroxide ◽  
Oxide Layer ◽  
Spectroscopic Ellipsometry ◽  
Chemical Deposition ◽  
Oxide Thickness ◽  
Electrical Performance ◽  
Signal To Noise ◽  
Rectification Factor ◽  
Mis Devices ◽  
The Ideal

AbstractIn this work we present results of a study performed on MIS diodes with the following structure: substrate (glass) / Cr (2000Å) / a-Si:H n+ (400Å) / a-Si:H i (5500Å) / oxide (0-40Å) / Au (100Å) to determine the influence of the oxide passivation layer grown by different techniques on the electrical performance of MIS devices. The results achieved show that the diodes with oxides grown using hydrogen peroxide present higher rectification factor (2×106)and signal to noise (S/N) ratio (1×107 at -1V) than the diodes with oxides obtained by the evaporation of SiO2, or by the chemical deposition of SiO2 by plasma of HMDSO (hexamethyldisiloxane), but in the case of deposited oxides, the breakdown voltage is higher, 30V instead of 3-10 V for grown oxides. The ideal oxide thickness, determined by spectroscopic ellipsometry, is dependent on the method used to grow the oxide layer and is in the range between 6 and 20 Å. The reason for this variation is related to the degree of compactation of the oxide produced, which is not relevant for applications of the diodes in the range of ± 1V, but is relevant when high breakdown voltages are required.

Effect of Illumination on Organic Polymer Thin-Film Transistors

2003 ◽  
Vol 771 ◽  
Author(s):  
Michael C. Hamilton ◽  
Sandrine Martin ◽  
Jerzy Kanicki
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Drain Current ◽  
Charge Carriers ◽  
Electrical Performance ◽  
Organic Polymer ◽  
Light Illumination ◽  
Polymer Thin Film ◽  
Channel Region ◽  
White Light Illumination

AbstractWe have investigated the effects of white-light illumination on the electrical performance of organic polymer thin-film transistors (OP-TFTs). The OFF-state drain current is significantly increased, while the drain current in the strong accumulation regime is relatively unaffected. At the same time, the threshold voltage is decreased and the subthreshold slope is increased, while the field-effect mobility of the charge carriers is not affected. The observed effects are explained in terms of the photogeneration of free charge carriers in the channel region due to the absorbed photons.

Materials Issues and Characterization of Low-k Dielectric Materials

MRS Bulletin ◽  
1997 ◽  
Vol 22 (10) ◽  
pp. 49-54 ◽  
Author(s):  
E. Todd Ryan ◽  
Andrew J. McKerrow ◽  
Jihperng Leu ◽  
Paul S. Ho
Keyword(s):  
Process Integration ◽  
Dielectric Materials ◽  
Propagation Delay ◽  
Thermomechanical Properties ◽  
General Criterion ◽  
Crosstalk Noise ◽  
Total Delay ◽  
Interlayer Dielectrics ◽  
Performance Improvements ◽  
And Performance

Continuing improvement in device density and performance has significantly affected the dimensions and complexity of the wiring structure for on-chip interconnects. These enhancements have led to a reduction in the wiring pitch and an increase in the number of wiring levels to fulfill demands for density and performance improvements. As device dimensions shrink to less than 0.25 μm, the propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant. Accordingly the interconnect delay now constitutes a major fraction of the total delay limiting the overall chip performance. Equally important is the processing complexity due to an increase in the number of wiring levels. This inevitably drives cost up by lowering the manufacturing yield due to an increase in defects and processing complexity.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILDs) and alternative architectures have surfaced to replace the current Al(Cu)/SiO2 interconnect technology. These alternative architectures will require the introduction of low-dielectric-constant k materials as the interlayer dielectrics and/or low-resistivity conductors such as copper. The electrical and thermomechanical properties of SiO2 are ideal for ILD applications, and a change to material with different properties has important process-integration implications. To facilitate the choice of an alternative ILD, it is necessary to establish general criterion for evaluating thin-film properties of candidate low-k materials, which can be later correlated with process-integration problems.

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