Evaluation and verification of enhanced electrical performance of advanced coreless flip-chip BGA package with warpage measurement data

Author(s):  
Ga Won Kim ◽  
Ji Heon Yu ◽  
Chul Woo Park ◽  
Seoung Joon Hong ◽  
Jin Young Kim ◽  
...  
2013 ◽  
Vol 2013 (1) ◽  
pp. 000478-000483
Author(s):  
Burton Carpenter ◽  
Boon Yew Low ◽  
Leo M. Higgins ◽  
Sriram Neelakantan ◽  
Robert Wenzel ◽  
...  

Next-generation processors continue to demand more thermal and electrical performance from the package. Frequently, devices are designed into Flip Chip (FC) packages where the previous generations were in Wire Bond (WB) because FC typically provides superior thermal dissipation and lower package electrical parasitics than WB packages. However, FC packages usually have higher costs for mid-range IO (500–800). An Enhanced WB BGA package has been designed with improved thermal and electrical performance compared to the industry standard TEPBGA-2 (Thermally Enhanced PBGA type 2). The 500μm barrier of mold compound between the die and heatspreader in the TEPBGA-2 is a major impediment to heat flow out of the package. By contrast, the Enhanced WB package uses post-mold attachment of a heat spreader that is adhesively bonded to the mold cap and thermally coupled to the die using a 40μm TIM (thermal interface material). Improvements to substrate design rules and the die attach process that enabled the Enhanced WB design to shorten bond wires by 40% and improved electrical performance. Package thermal resistance, Theta-Ja, was verified by simulation and measurement to be 3C°/W lower than TEPBGA-2, that dissipates up to 15W in some end-use applications, approximately 2× the performance of TEPBGA-2. DDR set-up and hold time showed 30ps improvement by both simulation and measurement. This paper will present the package design, thermal and electrical simulation and measurement results.


Author(s):  
Won-Keun Kim ◽  
Toru Ikeda ◽  
Noriyuki Miyazaki

Anisotropic Conductive Adhesive Film (ACF) has been used for electronic assemblies such as the connection between a Liquid Crystal Display (LCD) panel and a flexible print circuit board (FPC). ACF is expected to be a key technology for flip chip packaging and chip size packaging. The goal of our work is to provide an optimum design scheme to achieve the best combination of electrical performance and mechanical reliability for electronic packages using the ACF. This study presents an evaluation technology for the delamination of the ACF connections. We utilized the stress intensity factors of an interface crack between jointed dissimilar materials. The evaluation technology presented herein was found to provide reliability of an electronic package using the ACF connection during the solder reflow process.


Author(s):  
Peter Bodo ◽  
Hans Hentzell ◽  
Jan Strandberg ◽  
Joacim Haglund ◽  
Sima Valizadeh

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001937-001962
Author(s):  
Kai Liu ◽  
YongTaek Lee ◽  
HyunTai Kim ◽  
MaPhooPwint Hlaing ◽  
Susan Park ◽  
...  

In this paper, a 2-layer eWLB (embedded Wafer-Level BGA) is studied and its performance is compared with an equivalent 4-layer laminate package. Since eWLB package is processed by using lithographical method, design rules on width (W) and spacing (S) are much finer (usually 2–3 times finer) than those for laminate package. In other words, signal traces can be implemented in smaller fan-out regions. The smaller feature sizes for signal traces would end up with more metal loss per unit length. But as the signal traces can be implemented in smaller fan-out regions, overall trace-routing may be shorter, and equivalent insertion-loss may be achieved. In eWLB, the ground plane is closer to the signal traces. This actually helps to reduce cross-talk between wide I/O buses, as the electrical field is contained in a smaller region by the closer ground plane. Another key advantage from wafer-level package is a smoother metal surface, which greatly reduces the extra signal loss, due to surface-roughness effect, especially for higher-frequency and higher-speed applications. In addition, through-via structures for wafer-level package are typically 2–3 times smaller. This allows to implement power/ground planes in a more continuous way, achieving better resistance and inductance for power/ground nets. Overall electrical performance, which takes into account of all the impacts above, can be evaluated by signal-integrity analysis (E-diagram). Measurement data of a 2-layer eWLB package for a LPDDR application will be presented, which shows the comparable performance typically obtained from a 4-layer laminate package


2015 ◽  
Vol 2015 (CICMT) ◽  
pp. 000067-000072
Author(s):  
Bradley A. Thrasher ◽  
William E. McKinzie ◽  
Deepukumar M. Nair ◽  
Michael A. Smith ◽  
Allan Beikmohamadi ◽  
...  

Presented here are the design, fabrication, and measurement results of a low temperature cofired ceramic (LTCC) chip-to-interposer transition utilizing a flip-chip ball grid array (BGA) interconnect that provides excellent electrical performance up to and including 80 GHz. A test board fabricated in LTCC is used as the interposer substrate and another smaller LTCC part is used as a surrogate chip for demonstration purposes. The BGA chip-to-interposer transition is designed as a back-to-back pair of transitions with an assembly consisting of an LTCC interposer, an LTCC test chip, and a BGA interconnect constructed with 260 μm diameter polymer core solder balls. The LTCC material employed is DuPont™ GreenTape™ 9K7. Full-wave simulation results predict excellent electrical performance from 10 MHz to 80 GHz, with the chip-to-interposer BGA transition having less than 0.5 dB insertion loss at 60 GHz and less than 1 dB insertion loss up to 80 GHz. In an assembled package (back-to-back BGA transitions), the insertion loss was measured to be 1 dB per transition at 60 GHz and less than 2 dB per transition for all frequencies up to 80 GHz.


2010 ◽  
Vol 2010 (1) ◽  
pp. 000325-000332 ◽  
Author(s):  
Alan Huffman ◽  
Philip Garrou

As IC scaling continues to shrink transistors, the increased number of circuits per chip requires more I/O per unit area (Rent's rule). High I/O count, the need for smaller form factors and the need for better electrical performance drove the technological change towards die being interconnected (assembled) by area array techniques. This review will examine this evolution from die wire bonded on lead frames to flip chip die in wafer level or area array packages and discuss emerging technologies such as copper pillar bumps, fan out packaging, integrated passives, and 3D integration..


2011 ◽  
Vol 2011 (1) ◽  
pp. 000469-000475
Author(s):  
Rabindra N. Das ◽  
Frank D. Egitto ◽  
John M. Lauffer ◽  
Tim Antesberger ◽  
Voya R. Markovich

In this paper, the use of electrically conducting adhesives (ECA) to form z-axis interconnections for next generation packaging is discussed. In particular, current efforts related to Z-axis interconnections for device level fabrication, integration, and electrical performance are highlighted. A few optimized ECAs were used for hole fill applications to fabricate Z-axis interconnections in laminates. Conductive joints were formed during composite lamination using the ECA. Around 5,000 to 200,000 through holes in the joining cores, formed by laser or mechanical drilling, and having diameters ranging from 50 μm to 750 μm, were filled with an optimized conducting adhesive. The adhesive-filled joining cores/layers were laminated with circuitized subcomposites to produce a composite structure. As a case study, a variety of z-axis interconnect constructions for a flip-chip plastic ball grid array package, rigid-flex, rigid-rigid, package-interposer-package (PIP), RF structures, and PWBs were fabricated and evaluated at both the subcomposite and composite levels to understand structural and electrical integrity. Electrically, S-parameter measurements showed very low loss at multi-gigahertz frequencies. The losses were low enough to support typical SERDES up to 15 Gbps over 750 mm. The present process allows fabrication of z-interconnect conductive joints having diameters in the range of 55 to 500 μm. The processes and materials used to achieve smaller feature dimensions, satisfy stringent registration requirements, and achieve robust electrical interconnections are discussed.


2016 ◽  
Vol 2016 (1) ◽  
pp. 000321-000325
Author(s):  
Bob Chylak ◽  
Horst Clauberg ◽  
Tom Strothmann

Abstract Device packaging is undergoing a proliferation of assembly options within the ever-expanding category of Advanced Packaging. Fan Out-Wafer Level Packages are achieving wide adoption based on improved performance and reduced package size and new System in Package products are coming to market in FOWLP, 2.5D and 3D package formats with the full capability to leverage heterogeneous integration in small package profiles. While the wide-spread adoption of thermocompression bonding and 2.5D packages predicted several years ago has not materialized to the extent predicted, advanced memory modules assembled by TCB are in high volume manufacturing, as are some high-end GPUs with integrated memory on Si interposer. High accuracy flip chip has been pushed to fine pitches that were difficult to imagine only three years ago and innovation in substrates and bonder technology is pushing the throughput and pitch capability even further. The packaging landscape, once dominated by a few large assembly providers, now includes turn-key packaging initiatives from the foundries with an expanding set of fan-out packing options. The fan-out processes include face-up and face-down methods, die first and die last methods and 2.5D or 3D package options. Selection of the most appropriate packaging technology from the combined aspects of electrical performance, form-factor, yield and cost presents a complex problem with considerable uncertainty and high risk for capital investment. To address this problem, the industry demands flexible manufacturing solutions that can be modified and upgraded to accommodate a changing assembly environment. This presentation will present the assembly process flows for various packaging options and discuss the key aspects of the process that influence throughput, accuracy and other key quality metrics, such as package warpage. These process flows in turn impose design constraints on submodules of the bonder. It will be shown that thoughtfully designed machine architecture allows for interchangeable and upgradeable submodules that can support nearly the entire range of assembly options. As an example, a nimble, low weight, medium force, constant heat bondhead for high throughput FOWLP can be interchanged with a high force, pulse heater bondhead to support low stress/low warpage thermocompression bonding. The various configuration options for a flexible advanced packaging bonder will be reviewed along with the impact of configuration changes on throughput and accuracy.


2010 ◽  
Vol 2010 (1) ◽  
pp. 000847-000854 ◽  
Author(s):  
Rabindra N. Das ◽  
John M. Lauffer ◽  
Steven G. Rosser ◽  
Mark D. Poliks ◽  
Voya R. Markovich

This paper discusses thin film technology based on barium titanate (BaTiO3)-epoxy polymer nanocomposites. In particular, we highlight recent developments on high capacitance, large area, thin film passives and their integration in System in a Package (SiP). A variety of nanocomposite thin films ranging from 2 microns to 25 microns thick were processed on PWB substrates by liquid coating or printing processes. SEM micrographs showed uniform particle distribution in the coatings. The electrical performance of composites was characterized by dielectric constant (Dk), capacitance and dissipation factor (loss) measurements. We have designed and fabricated several printed wiring board (PWB) and flip-chip package test vehicles focusing on resistors and capacitors. Two basic capacitor cores were used for this study. One is a layer capacitor. The second capacitor in this case study was discrete capacitor. Resin Coated Copper Capacitive (RC3) nanocomposites were used to fabricate 35 mm substrates with a two by two array of 15mm square isolated epoxy based regions; each having two to six RC3 based embedded capacitance layers. Cores are showing high capacitance density ranging from 15 nF to 30nF depending on Cu area, composition and thickness of the capacitors. In another design, we have used eight layer high density internal core and subsequent fine geometry n (1 to 3) buildup layers to form a n-8-n structure. The eight layer internal core has two resistance layers in the middle and 2 to 6 capacitance layer sequentially applied on the surface. The study also evaluates the resistor materials for embedded passives. Resistors are carbon based pastes and metal based alloys NiCrAlSi. Embedded resistor technology can use either thin film materials, that are applied on the copper foil, or screened carbon based resistor pastes that can achieve any resistor value at any level. For example, combination of 25 ohm per square material and 250 ohm per square material enables resistor ranges from 15 ohms through 30,000 ohms with efficient sizes for the embedded resistors. Similarly, printable resistors can be designed to cover the resistance in the range of 5 ohms to 1 Mohm. The embedded resistors can be laser trimmed to a tolerance of <5% for applications that require tighter tolerance. Reliability of the test vehicles was ascertained by IR-reflow, thermal cycling, PCT (Pressure Cooker Test ) and solder shock. Embedded discrete capacitors were stable after PCT and solder shock. Capacitance change was less than 5% after IR reflow (assembly) preconditioning (3X, 245 °C) and 1400 cycles DTC (Deep Thermal Cycle).


Sign in / Sign up

Export Citation Format

Share Document