Thermally and Electrically Enhanced Wirebond BGA

2013 ◽  
Vol 2013 (1) ◽  
pp. 000478-000483
Author(s):  
Burton Carpenter ◽  
Boon Yew Low ◽  
Leo M. Higgins ◽  
Sriram Neelakantan ◽  
Robert Wenzel ◽  
...  
Keyword(s):  
Flip Chip ◽  
Hold Time ◽  
Thermal Interface Material ◽  
Thermal Dissipation ◽  
Electrical Performance ◽  
Package Design ◽  
Die Attach ◽  
Bga Package ◽  
End Use ◽  
Set Up

Next-generation processors continue to demand more thermal and electrical performance from the package. Frequently, devices are designed into Flip Chip (FC) packages where the previous generations were in Wire Bond (WB) because FC typically provides superior thermal dissipation and lower package electrical parasitics than WB packages. However, FC packages usually have higher costs for mid-range IO (500–800). An Enhanced WB BGA package has been designed with improved thermal and electrical performance compared to the industry standard TEPBGA-2 (Thermally Enhanced PBGA type 2). The 500μm barrier of mold compound between the die and heatspreader in the TEPBGA-2 is a major impediment to heat flow out of the package. By contrast, the Enhanced WB package uses post-mold attachment of a heat spreader that is adhesively bonded to the mold cap and thermally coupled to the die using a 40μm TIM (thermal interface material). Improvements to substrate design rules and the die attach process that enabled the Enhanced WB design to shorten bond wires by 40% and improved electrical performance. Package thermal resistance, Theta-Ja, was verified by simulation and measurement to be 3C°/W lower than TEPBGA-2, that dissipates up to 15W in some end-use applications, approximately 2× the performance of TEPBGA-2. DDR set-up and hold time showed 30ps improvement by both simulation and measurement. This paper will present the package design, thermal and electrical simulation and measurement results.

Experimental and Numerical Investigation of the Reliability of Double-Sided Area Array Assemblies

2006 ◽  
Vol 128 (4) ◽  
pp. 441-448 ◽  
Author(s):  
S. Chaparala ◽  
J. M. Pitarresi ◽  
S. Parupalli ◽  
S. Mandepudi ◽  
M. Meilunas
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Mirror Image ◽  
Circuit Board ◽  
Thermal Dissipation ◽  
Electrical Performance ◽  
Area Array ◽  
Plastic Ball

One of the primary advantages of surface mount technology (SMT) over through-hole technology is that SMT allows the assembly of components on both sides of the printed circuit board (PCB). Currently, area array components such as ball grid array (BGA) and chip-scale package (CSP) assemblies are being used in double-sided configurations for network and memory device applications as they reduce the routing space and improve electrical performance (Shiah, A. C., and Zhou, X., 2002, “A Low Cost Reliability Assessment for Double-Sided Mirror-Imaged Flip Chip BGA Assemblies,” Proceedings of the Seventh Annual Pan Pacific Microelectronics Symposium, Maui, Hawaii, pp. 7–15, and Xie, D., and Yi, S., 2001, “Reliability Design and Experimental work for Mirror Image CSP Assembly”, Proceedings of the International Symposium on Microelectronics, Baltimore, October, pp. 417–422). These assemblies typically use a “mirror image” configuration wherein the components are placed on either side of the PCB directly over each other; however, other configurations are possible. Double-sided assemblies pose challenges for thermal dissipation, inspection, rework, and thermal cycling reliability. The scope of this paper is the study of the reliability of double-sided assemblies both experimentally and through numerical simulation. The assemblies studied include single-sided, mirror-imaged, 50% offset CSP assemblies, CSPs with capacitors on the backside, single-sided, mirror-imaged plastic ball grid arrays (PBGAs), quad flat pack (QFP)/BGA mixed assemblies. The effect of assembly stiffness on thermal cycling reliability was investigated. To assess the assembly flexural stiffness and its effect on the thermal cycling reliability, a three-point bending measurement was performed. Accelerated thermal cycling cycles to failure were documented for all assemblies and the data were used to calculate the characteristic life. In general, a 2X to 3X decrease in reliability was observed for mirror-image assemblies when compared to single-sided assemblies for both BGAs and CSPs on 62mil test boards. The reliability of mirror-image assemblies when one component was an area array device and the other was a QFP was comparable to the reliability of the single-sided area array assemblies alone, that is, the QFP had almost no influence on the double-sided reliability when used with an area array component. Moiré interferometry was used to study the displacement distribution in the solder joints at specific locations in the packages. Data from the reliability and moiré measurements were correlated with predictions generated from three-dimensional finite element models of the assemblies. The models incorporated nonlinear and time-temperature dependent solder material properties and they were used to estimate the fatigue life of the solder joints and to obtain an estimate of the overall package reliability using Darveaux’s crack propagation method.

Applicability of Existing Reliability Models: Focus on Finite Element Modeling of Various BGA Package Designs and Materials

2011 ◽  
Vol 2011 (1) ◽  
pp. 000223-000231
Author(s):  
Ali Fallah-Adl ◽  
Amaneh Tasooji ◽  
Ravi Mahajan ◽  
Nachiket Raravikar ◽  
Richard Harries ◽  
...  
Keyword(s):  
Finite Element ◽  
Flip Chip ◽  
Solder Joints ◽  
State University ◽  
Arizona State University ◽  
Element Analysis ◽  
Package Design ◽  
Reliability Models ◽  
Bga Package ◽  
Global And Local

The work presented here is one of the key elements of an integrated methodology for predicting reliability in packaging systems (IMPRPK) developed by Arizona State University (ASU) and Intel. IMPRPK approach is based on a probabilistic methodology, focusing on three major tasks: (1) Finite Element analysis (FEM) to predict loading conditions, (2) Characterization of BGA solder joints to identify failure mechanisms and obtain statistical data, and (3) development of a probabilistic methodology to achieve an integrated reliability solution. The focus of this paper is on FEM (task 1), evaluating the effect of package design/form-factor and solder materials on the extent of deformation (e.g., inelastic stress/strain and strain energy density) experienced by BGA solder joints. Global and Local FEM results for two different package designs (Flip-chip and wire-bonded FLI) and two different BGA solder materials (lead-free SAC405 and lead-rich eutectic Sn37Pb) are discussed. The FEM results and the applicability of the existing reliability models (e.g., energy-based model) to the complex microelectronics packaging systems are validated through independent comparison with the accelerated thermal cycled (ATC) test data.

Co-optimized Reliability and Parasitic inductance in Small Footprint Vertical Silicon Carbide MOSFET

2018 ◽  
Vol 2018 (HiTEC) ◽  
pp. 000087-000092
Author(s):  
M. Montazeri ◽  
S. Seal ◽  
A. Wallace ◽  
A. Mantooth ◽  
D. Huitink
Keyword(s):  
Silicon Carbide ◽  
Thermal Cycling ◽  
Power Electronics ◽  
Flip Chip ◽  
Thermal Dissipation ◽  
Electrical Performance ◽  
Element Analysis ◽  
Great Opportunity ◽  
Parasitic Inductance ◽  
Fea Simulation

Abstract Increasing power density in power electronics is driving a need for improved packaging methods for co-optimized high frequency performance, thermal dissipation and reliable operation, especially at high temperatures. Silicon Carbide (SiC) devices offer great opportunity as wide bandgap semiconductor devices, which maintain stability over wide temperature ranges, especially when compared to Silicon (Si) based devices. A novel flip-chip packaging technique for SiC power devices was developed at the University of Arkansas. This new package re-orients a bare die from a lateral device to a vertical device by utilizing a copper connector that routes the drain connection to the top side of the die. This study involves an investigation of achieving a co-optimized packaging configuration for thermomechanical reliability and low parasitic inductance. By orienting this SiC switch vertically, the unique 3D drain connector dramatically reduces the ringing at aggressive switching speeds used in power electronics when compared to Commercial Off The Shelf (COTS) devices. However, the design of this drain connector holds importance for high temperature operation, interconnect reliability as well as manufacturability. Effects of the packaging design, including materials, layout and solder pitch size were investigated from a thermal cycling reliability aspect. Electrical performance, such as parasitic inductances of the device, was also investigated using Finite Element Analysis (FEA) simulation. Several drain connector architectures were evaluated for their fatigue life capability of solder interconnects under thermal cycling (according to Darveaux's model) in conjunction with the parasitic inductance using FEA simulation. Based on the simulation results, an optimized architecture was selected and fabricated for prototype demonstration, and the electrical performance under double pulse test compared with state of the art devices demonstrated improvement in switching performance by reducing overshoot of voltage across the grain-source by 36% and 77% reduction of the drain current ringing during the turn-off event while eliminating voltage overshoot during turn-on event for the testing conditions.

Development of Reliable Electronic Packaging Solutions for Spacecraft Avionics Miniaturization Using Embedded Passive Devices

2003 ◽  
Author(s):  
Don Schatzel
Keyword(s):  
Thin Film ◽  
Thermal Cycling ◽  
Electronic Packaging ◽  
Flip Chip ◽  
Dielectric Materials ◽  
Electrical Performance ◽  
Passive Devices ◽  
Die Attach ◽  
Space Environments ◽  
Viable Approach

Miniaturization of electronic packages will play a key role in future space avionics systems. Smaller avionics packages will reduce payloads while providing greater functionality for information processing and mission instrumentation. Current surface mount technology discrete passive devices not only take up significant space but also add weight. To that end, the use of embedded passive devices, such as capacitors, inductors and resistors will be instrumental in allowing electronics to be made smaller and lighter. Embedded passive devices fabricated on silicon or like substrates using thin film technology, promise great savings in circuit volume, as well as potentially improving electrical performance by decreasing parasitic losses. These devices exhibit a low physical profile and allow the circuit footprint to be reduced by stacking passive elements within a substrate. Thin film technologies used to deposit embedded passive devices are improving and costs associated with the process are decreasing. There are still many challenges with regard to this approach that must be overcome. In order to become a viable approach these devices need to work in conjunction with other active devices such as bumped die (flip chip) that share the same substrate area. This dictates that the embedded passive devices are resistant to the subsequent assembly processes associated with die attach (temperature, pressure). Bare die will need to be mounted directly on top of one or more layers of embedded passive devices. Currently there is not an abundant amount of information available on the reliability of these devices when subjected to the high temperatures of die attach or environmental thermal cycling for space environments. Device performance must be consistent over time and temperature with minimal parasitic loss. Pretested and assembled silicon substrates with layers of embedded capacitors made with two different dielectric materials, Ta2O5 (Tantalum Oxide) and benzocyclobutene (BCB), were subjected to the die attach process and tested for performance in an ambient environment. These assemblies were subjected to environmental thermal cycling from −55°C to 100°C. Preliminary results indicate embedded passive capacitors and resistors can fulfill the performance and reliability requirements of space flight on future missions. Testing results are encouraging for continued development of integrating embedded passive devices to replace conventional electronic packaging methods.

Characterizing and Minimizing Voids in Quad Flat No-Lead Pack (QFN) Device Assembly Using Pb-Free Solder Alloys

2009 ◽  
Author(s):  
Rangaraj Dhanasekaran ◽  
Harish Gadepalli ◽  
S. Manian Ramkumar ◽  
Tim Jensen ◽  
Ed Briggs
Keyword(s):  
Void Formation ◽  
Primary Objective ◽  
Thermal Dissipation ◽  
Electrical Performance ◽  
Solder Paste ◽  
Die Attach ◽  
Aperture Opening ◽  
Free Solder ◽  
Small Form Factor ◽  
The Impact

Quad Flatpack No lead (QFN) packages have become a popular choice in electronics packaging due to its small form factor. They are also gaining rapid industry acceptance because of its excellent thermal and electrical performance. The bottom side of the QFN package has a large thermal pad. This exposed die attach pad effectively conducts heat to the PCB and also provides a stable ground connection. Effective soldering of this surface to the pad on the PCB is required for good thermal dissipation and component functionality. The exposed thermal pad presents various challenges during the surface mount assembly process. One major challenge is solder void formation. Voids are primarily formed due to the entrapment of volatiles in flux outgassing during the reflow process. The primary objective of this study is to determine optimal parameters to minimize void formation in QFN packages (QFN16, QFN20, QFN28 and QFN32), specifically the reflow profile, lead-free solder paste and stencil aperture opening for the thermal pad. A systematic DOE based approach was used to arrive at conclusions, using the ratio of void volume on the thermal pad to the actual volume of solder paste printed as the response variable. Various graphs are presented to understand the impact of different parameters. Interaction graphs are used to determine optimal settings for each parameter.

Flip-chip Packages with Periphery Cu Pillar Bumps as Wire Bond Replacement—Design, Modeling & Characterization

2013 ◽  
Vol 2013 (1) ◽  
pp. 000235-000235
Author(s):  
Zhe Li ◽  
Siow Chek Tan ◽  
Yee Huan Yew ◽  
Pheak Ti Teh ◽  
MJ Lee ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
Flip Chip ◽  
Low Cost ◽  
Electrical Performance ◽  
Package Design ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Field Programmable ◽  
Small Form Factor

Cu pillar is an emerging interconnect technology which offers many advantages compared to traditional packaging technologies. This paper presents a novel packaging solution with periphery fine pitch Cu pillar bumps for low cost and high performance Field Programmable Gate Array (FPGA) devices. Wire bonding has traditionally been the choice for low cost implementation of memory interfaces and high speed transceivers. Migration to Cu pillar technology is mainly driven by increasing demand for IO density and package small form factor. Cu pillar bumps also offer significant improvement on electrical performance compared to wire bonds. This paper presents Cu pillar implementation in an 11×11mm flip chip CSP package. Package design is optimized for serial data transport up to 6.114Gbps to meet CPRI_LVII and PCIe Gen2 compliance requirements. Package design strategy includes die and package co-design, SI/PI modeling and physical layout optimization.

Application of an Epoxy Cap in a Flip-Chip Package Design

1989 ◽  
Vol 111 (1) ◽  
pp. 16-20 ◽  
Author(s):  
E. Suhir
Keyword(s):  
Thermal Expansion ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Preliminary Test ◽  
Elastic Stability ◽  
Thermally Induced ◽  
Package Design ◽  
Silicone Gels ◽  
Low Modulus ◽  
Supporting Frame

In order to combine the merits of epoxies, which provide good environmental and mechanical protection, and the merits of silicone gels, resulting in low stresses, one can use an encapsulation version, where a low modulus gel is utilized as a major encapsulant, while epoxy is applied as a protecting cap. Such an encapsulation version is currently under consideration, parallel with a metal cap version, for the Advanced VLSI package design which is being developed at AT&T Bell Laboratories. We recommend that the coefficient of thermal expansion for the epoxy be somewhat smaller than the coefficient of thermal expansion for the supporting frame. In this case the thermally induced displacements would result in a desirable tightness in the cap/frame interface. This paper is aimed at the assessment of stresses, which could arise in the supporting frame and in the epoxy cap at low temperatures. Also, the elastic stability of the cap, subjected to compression, is evaluated. The calculations were executed for the Advanced VLSI package design and for a Solder Test Vehicle (STV), which is currently used to obtain preliminary information regarding the performance of the candidate encapsulants. It is concluded that in order to avoid buckling of the cap, the latter should not be thinner than 15 mils (0.40 mm) in the case of VLSI package design and than 17.5 mils (0.45 mm) in the case of STV. At the same time, the thickness of the cap should not be greater than necessary, both for smaller stresses in the cap and for sufficient undercap space, required for wirebond encapsulation. The obtained formulas enable one to evaluate the actual and the buckling stresses. Preliminary test data, obtained by using STV samples, confirmed the feasibility of the application of an epoxy cap in a flip-chip package design.

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