USING PERCOLATIVE CRYSTALLINE 0.3 CUO/PVDF NANOCOMPOSITE GATE DIELECTRIC FOR FABRICATING HIGH-EFFECT MOBILITY THIN FILM TRANSISTOR OPERATING AT LOW VOLTAGE

Thin-film transistor (TFT) with various layers of crystalline Poly-vinylidene fluoride (PVDF)/CuO percolative nanocomposites based on Anthracene as a gate dielectric insulator have been fabricated. A device with excellent electrical characteristics at low operating voltages (<1V) has been designed. Different layers (L) of the film were also prepared to achieve the best optimization of ideal gate insulator with various static dielectric constants (εr). Capacitance density, leakage current at 1V gate voltage and electrical characteristics of OFETs with a single and multi layer films have been investigated. This device was showed highest field effect mobility of 2.27 cm2/Vs, a threshold voltage of -1.6V, an exceptionally low sub threshold slope of 380 mV/decade and an on/off ratio of 106. Such a High-ε three layered (3L) PVDF/CuO gate dielectric appears to be highly promising candidates for organic non-volatile memory, sensor and field-effect transistors (FETs).

An Optimum Structure of Scalable Capacitors in 3D Crosspoint Memory Technology

Memory chips need large capacitors in their periphery to drive boosted word-lines and bit-lines for read and write operations. In a previous work, scalable capacitors were proposed for 3D crosspoint memory to keep the area for the capacitors constant over technology generations. This paper proposes the capacitance models of three types of wiring capacitors: (1) vertical capacitor, (2) vertical and horizontal capacitor with next-neighbor wires connected with the other terminal, and (3) vertical and horizontal capacitor with next-neighbor pairs connected with the other terminal. These models are based on Wong’s crossover capacitor model to determine the capacitor structure with the highest capacitance density in 3D crosspoint memory technology. One can determine the best structure through optimizing the process parameters such as the height H of the insulation material between the metal wires and the thickness T of the metal wires and the design rules such as the width W and space S of metal wires. The model accuracy was in good agreement with the measurement of twelve types of capacitor structures fabricated in a 180 nm 6 metal standard CMOS process with the maximum error of 20%. Contour plots of the capacitance density across H vs. S where it is assumed that W = T = S are shown. As a result, the boundary condition regarding H and S is determined per 3D crosspoint memory technology with three, four, or five levels of wires.

A Highly Tunable Barium Strontium Titanate Thin Film MIM Varactor With Floating Metal

A ferroelectric metal insulator metal (MIM) varactor structure incorporating a floating metal and coplanar waveguide (CPW) has been introduced here. The work of the proposed varactor is based on the field-dependent material properties of (Ba,Sr)TiO3 (BST) thin film. A capacitance tunability of 44% has been achieved for the bias voltage of 0 V to 10 V over a frequency range of 1 GHz to 3 GHz. The proposed varactor structure yields a compact area, high capacitance density, and reduced mask process (2 masks)

A Highly Tunable Barium Strontium Titanate Thin Film MIM Varactor With Floating Metal

A ferroelectric metal insulator metal (MIM) varactor structure incorporating a floating metal and coplanar waveguide (CPW) has been introduced here. The work of the proposed varactor is based on the field-dependent material properties of (Ba,Sr)TiO3 (BST) thin film. A capacitance tunability of 44% has been achieved for the bias voltage of 0 V to 10 V over a frequency range of 1 GHz to 3 GHz. The proposed varactor structure yields a compact area, high capacitance density, and reduced mask process (2 masks)

Fabrication of Silicon Nanowire Metal-Oxide-Semiconductor Capacitors with Al2O3/TiO2/Al2O3 Stacked Dielectric Films for the Application to Energy Storage Devices

Silicon nanowire (SiNW) metal-oxide-semiconductor (MOS) capacitors with Al2O3/TiO2/Al2O3 (ATA) stacked dielectric films were fabricated by metal-assisted chemical etching (MACE) and atomic layer deposition (ALD). High-angle annular dark field scanning transmission electron microscopy (HAADF-STEM) images revealed that SiNWs were conformally coated with ATA although the cross-sectional shapes of MACE-SiNWs were non-uniform and sharp spikes can be seen locally. The dielectric capacitance density of 5.9 μF/cm2 at V = −4 V of the perfect accumulation region was achieved due to the combination of the large surface area of the SiNW array and the high dielectric constant of ATA. The capacitance changed exponentially with the voltage at V < −4.3 V and the capacitance of 84 μF/cm2 was successfully achieved at V = −10 V. It was revealed that not only 3D structure and high-k material but also local nanostructure of SiNWs and stacked dielectric layers could contribute to the considerable high capacitance.

Tomographic Proximity Imaging Using Conductive Sheet for Object Tracking

This paper proposes a proximity imaging sensor based on a tomographic approach with a low-cost conductive sheet. Particularly, by defining capacitance density, physical proximity information is transformed into electric potential. A novel theoretical model is developed to solve the capacitance density problem using the tomographic approach. Additionally, a prototype is built and tested based on the model, and the system solves an inverse problem for imaging the capacitance density change that indicates the object’s proximity change. In the evaluation test, the prototype reaches an error rate of 10.0–15.8% in horizontal localization at different heights. Finally, a hand-tracking demonstration is carried out, where a position difference of 33.8–46.7 mm between the proposed sensor and depth camera is achieved at 30 fps.

Stacking Cell Model Supercapacitor Asymmetry with Multilayer Reduced Graphene Oxide Films Fabricated Using UV Oven Spraying Technique

We report the fabrication of multilayer reduced graphene oxide films using UV oven spraying technique for stacking cell model supercapacitor asymmetry. In report, we used nickel and carbon substrates as asymmetric current collectors. Using UV oven spraying technique, graphene oxide was coated and insitu converted on substrate surfaces forming reduced graphene oxide films that act as active materials in supercapacitor asymmetry. The films consist of 70 layers with delay time between consecutive layer prior to irradiation is 4 minutes to ensure the photoreduction take place on each layer. UV light source using Mercury lamp 125 watt at 30 cm above the substrates. The model structures consist of three cells stacked serial in 1M KCl electrolyte system. Device performance was characterized using charge-discharge technique for constant current at 2, 3, 4, 5, and 10 mA. Performance parameters are the capacitance density, power and energy density. Single cell supercapacitor has energy density in range of 0.072 Wh/kg to 0.256 Wh/kg and power density in range of 123.06 W/kg to 644.14 W/kg. Meanwhile for stacked cell supercapacitor has energy density in range of 0.377 Wh/kg to 0.755 Wh/kg, and power density in range of 169.95 W/kg to 849.79 W/kg. According to Ragone Plot, the results have feature as supercapacitor, even as single cell. Stacked cell has feature better than single cell in all parameter of capacitance density, power and energy density, and electrical working potential.