Robust PoP probing solutions for high-performance application processor developments

Author(s):  
Weiliang Yuan ◽  
SungJoo Kim ◽  
Woong Hwan Ryu ◽  
SeongJae Moon ◽  
Sangmin Lee
2019 ◽  
Vol 6 (1) ◽  
Author(s):  
Mahdi Torabzadehkashi ◽  
Siavash Rezaei ◽  
Ali HeydariGorji ◽  
Hosein Bobarshad ◽  
Vladimir Alves ◽  
...  

AbstractIn the era of big data applications, the demand for more sophisticated data centers and high-performance data processing mechanisms is increasing drastically. Data are originally stored in storage systems. To process data, application servers need to fetch them from storage devices, which imposes the cost of moving data to the system. This cost has a direct relation with the distance of processing engines from the data. This is the key motivation for the emergence of distributed processing platforms such as Hadoop, which move process closer to data. Computational storage devices (CSDs) push the “move process to data” paradigm to its ultimate boundaries by deploying embedded processing engines inside storage devices to process data. In this paper, we introduce Catalina, an efficient and flexible computational storage platform, that provides a seamless environment to process data in-place. Catalina is the first CSD equipped with a dedicated application processor running a full-fledged operating system that provides filesystem-level data access for the applications. Thus, a vast spectrum of applications can be ported for running on Catalina CSDs. Due to these unique features, to the best of our knowledge, Catalina CSD is the only in-storage processing platform that can be seamlessly deployed in clusters to run distributed applications such as Hadoop MapReduce and HPC applications in-place without any modifications on the underlying distributed processing framework. For the proof of concept, we build a fully functional Catalina prototype and a CSD-equipped platform using 16 Catalina CSDs to run Intel HiBench Hadoop and HPC benchmarks to investigate the benefits of deploying Catalina CSDs in the distributed processing environments. The experimental results show up to 2.2× improvement in performance and 4.3× reduction in energy consumption, respectively, for running Hadoop MapReduce benchmarks. Additionally, thanks to the Neon SIMD engines, the performance and energy efficiency of DFT algorithms are improved up to 5.4× and 8.9×, respectively.


2015 ◽  
Vol 21 (6) ◽  
pp. 630-648 ◽  
Author(s):  
Sunil Kumar Tiwari ◽  
Sarang Pande ◽  
Sanat Agrawal ◽  
Santosh M. Bobade

Purpose – The purpose of this paper is to propose and evaluate the selection of materials for the selective laser sintering (SLS) process, which is used for low-volume production in the engineering (e.g. light weight machines, architectural modelling, high performance application, manufacturing of fuel cell, etc.), medical and many others (e.g. art and hobbies, etc.) with a keen focus on meeting customer requirements. Design/methodology/approach – The work starts with understanding the optimal process parameters, an appropriate consolidation mechanism to control microstructure, and selection of appropriate materials satisfying the property requirement for specific application area that leads to optimization of materials. Findings – Fabricating the parts using optimal process parameters, appropriate consolidation mechanism and selecting the appropriate material considering the property requirement of applications can improve part characteristics, increase acceptability, sustainability, life cycle and reliability of the SLS-fabricated parts. Originality/value – The newly proposed material selection system based on properties requirement of applications has been proven, especially in cases where non-experts or student need to select SLS process materials according to the property requirement of applications. The selection of materials based on property requirement of application may be used by practitioners from not only the engineering field, medical field and many others like art and hobbies but also academics who wish to select materials of SLS process for different applications.


This work investigates the performance of SiGe Hybrid JunctionLess FinFET (HJLFinFET) on insulator with different mole fraction x. The band gap difference for different mole fractions are explored. Impact of electrical characteristics and SCE of HJLFinFET are analyzed with fin width 10nm and varying gate length from 5nm-40nm for different mole fraction. Synopsys Sentaurus TCAD tool(sprocess and sdevice) are used in Device modelling and device simulation. Simulation results shows improvement in On current, DIBL and SS. For high performance application SiGe with mole fraction less than 0.3 at channel length less than 10nm are suitable because of the bandgap value is similar to silicon.


2018 ◽  
Vol 17 (2) ◽  
pp. 43-50
Author(s):  
Al-Mayhedee Zubair ◽  
Mohammad Abdul Mannan ◽  
Junji Tamura

The environment friendly blessings of Electrical Vehicles (EV), human beings are becoming extra involved in the use of them alternatively than the usage of mechanical differentials. In electrical vehicles distinct sorts of electrical machines are used among them DFIM is used in this work. The challenging work is to design of a controller as the output of the motor has to match with vehicle input. So, far, most of the mentioned works have utilized Proportional-Integral (PI) controllers as the speed control. But, the negative aspects of PI controller are properly known, as its design depends on the specific motor parameters and the overall performance is sensitive to system disturbances. The fundamental goal of this paper is to replace the conventional PI controller by means of an IP controller which is successful of dealing with exceedingly non-linear DFIM motor for high performance application in Electrical Vehicle. The effectiveness of designed IP controller of an electrical differential for an EV system is evaluated through Matlab/Simulink software. In simulation work different road conditions for EV are considered. After the simulation the designed controller is found to be strong for the speed control application of Electrical Vehicle.


2013 ◽  
Vol 2013 (1) ◽  
pp. 000414-000414 ◽  
Author(s):  
Noriyoshi Shimizu ◽  
Wataru Kaneda ◽  
Hiromu Arisaka ◽  
Naoyuki Koizumi ◽  
Satoshi Sunohara ◽  
...  

In recent years, it has become apparent that the conventional FC-BGA (Flip Chip Ball Grid Array) substrate manufacturing method (Electroless Cu plating, Desmear, Laser Drilling processing) is reaching its limits for finer wiring dimensions and narrower pitches of the flip chip pad. On the other hand, the demand for miniaturization and higher density continues to increase. Our solution is the Organic Multi Chip Package, a combined organic interposer and organic substrate. Unlike a conventional 2.5D interposer that is separately manufactured and then attached to a substrate PWB (Printed Wire Board), the interposer of our Organic Multi Chip Package is built directly onto an organic substrate. First normal build-up layers are laminated on both sides of the PWB core and metal traces formed by conventional semi-additive techniques. After the back side is coated with a typical SR layer for FC-BGA, the top surface and its laser-drilled vias are smoothed by CMP (Chemical Mechanical Polishing). A thin-film process is used to deposit the interposer's insulating resin layers. Then normal processes are applied to open small diameter vias and a metal seed layer is sputtered on. The wiring is patterned, and the metal traces are fully formed by plating. Finally, the Cu pads on the top layer are treated by OSP (Organic Solderability Preservative). In this paper we discuss results using a prototype 40 mm × 40 mm Organic Multi Chip Package. The prototype's organic substrate has a two-metal layer core with 100 μm diameter through-holes, two build-up layers on the chip side, and three plus a solder resist layer on the BGA side. The interposer has four wiring layers. Thus the structure of the prototype is 4+(2/2/3). For evaluation purposes, there are four patterns of lines and spaces on the interposer: 2 μm/2 μm, 3 μm/3 μm, 4 μm/4 μm, and 5 μm/5 μm. The metal trace thicknesses are 2.5 μm, via diameters are 10 μm, pad pitches are 40 μm, and the Cu pad diameters are 25 μm. These dimensions allow the Organic Multi Chip Package to easily make the pitch conversions of the IC to the PCB. With a 4+(2/2/3) structure, the Organic Multi Chip Package is asymmetric, raising concerns about package warping. However, the warping can be reduced by the optimization of structure and materials. In this way, we were able to connect a high pin-count logic chip to standard Wide I/O memory chips. We think that there are at least two obvious advantages of the Organic Multi Chip Package. The first is a total height reduction compared to a structure with a separate silicon interposer attached to a PWB substrate. The Organic Multi Chip Package, with its built-on interposer, eliminates the need for solder joints between the interposer and substrate. In addition, the fine resin layers make our interposer much thinner than a silicon interposer. The second advantage is simpler assembly. Our structure does not require the separate step of assembling an interposer to the substrate. Assembly costs should be lower and yields higher. In this paper we demonstrate the successful attainment of fine lines and spaces on the Organic Multi Chip Package. We also show and discuss reliability test results.


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