Development of Organic Multi Chip Package for High Performance Application

2013 ◽  
Vol 2013 (1) ◽  
pp. 000414-000414 ◽  
Author(s):  
Noriyoshi Shimizu ◽  
Wataru Kaneda ◽  
Hiromu Arisaka ◽  
Naoyuki Koizumi ◽  
Satoshi Sunohara ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Metal Layer ◽  
Small Diameter ◽  
Organic Substrate ◽  
Back Side ◽  
Test Results ◽  
Manufacturing Method ◽  
Separate Step ◽  
High Performance Application

In recent years, it has become apparent that the conventional FC-BGA (Flip Chip Ball Grid Array) substrate manufacturing method (Electroless Cu plating, Desmear, Laser Drilling processing) is reaching its limits for finer wiring dimensions and narrower pitches of the flip chip pad. On the other hand, the demand for miniaturization and higher density continues to increase. Our solution is the Organic Multi Chip Package, a combined organic interposer and organic substrate. Unlike a conventional 2.5D interposer that is separately manufactured and then attached to a substrate PWB (Printed Wire Board), the interposer of our Organic Multi Chip Package is built directly onto an organic substrate. First normal build-up layers are laminated on both sides of the PWB core and metal traces formed by conventional semi-additive techniques. After the back side is coated with a typical SR layer for FC-BGA, the top surface and its laser-drilled vias are smoothed by CMP (Chemical Mechanical Polishing). A thin-film process is used to deposit the interposer's insulating resin layers. Then normal processes are applied to open small diameter vias and a metal seed layer is sputtered on. The wiring is patterned, and the metal traces are fully formed by plating. Finally, the Cu pads on the top layer are treated by OSP (Organic Solderability Preservative). In this paper we discuss results using a prototype 40 mm × 40 mm Organic Multi Chip Package. The prototype's organic substrate has a two-metal layer core with 100 μm diameter through-holes, two build-up layers on the chip side, and three plus a solder resist layer on the BGA side. The interposer has four wiring layers. Thus the structure of the prototype is 4+(2/2/3). For evaluation purposes, there are four patterns of lines and spaces on the interposer: 2 μm/2 μm, 3 μm/3 μm, 4 μm/4 μm, and 5 μm/5 μm. The metal trace thicknesses are 2.5 μm, via diameters are 10 μm, pad pitches are 40 μm, and the Cu pad diameters are 25 μm. These dimensions allow the Organic Multi Chip Package to easily make the pitch conversions of the IC to the PCB. With a 4+(2/2/3) structure, the Organic Multi Chip Package is asymmetric, raising concerns about package warping. However, the warping can be reduced by the optimization of structure and materials. In this way, we were able to connect a high pin-count logic chip to standard Wide I/O memory chips. We think that there are at least two obvious advantages of the Organic Multi Chip Package. The first is a total height reduction compared to a structure with a separate silicon interposer attached to a PWB substrate. The Organic Multi Chip Package, with its built-on interposer, eliminates the need for solder joints between the interposer and substrate. In addition, the fine resin layers make our interposer much thinner than a silicon interposer. The second advantage is simpler assembly. Our structure does not require the separate step of assembling an interposer to the substrate. Assembly costs should be lower and yields higher. In this paper we demonstrate the successful attainment of fine lines and spaces on the Organic Multi Chip Package. We also show and discuss reliability test results.

Development of 3D System-in-Package with TSV Technology

2014 ◽  
Vol 2014 (1) ◽  
pp. 000612-000617 ◽  
Author(s):  
Shota Miki ◽  
Takaharu Yamano ◽  
Sumihiro Ichikawa ◽  
Masaki Sanada ◽  
Masato Tanaka
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Organic Substrate ◽  
Back Side ◽  
Final Thickness ◽  
Chip Technology ◽  
Type Semiconductor ◽  
Interconnect Reliability ◽  
Solder Balls ◽  
Carrier Wafer

In recent years, products such as smart phones, tablets, and wearable devices, are becoming miniaturized and high performance. 3D-type semiconductor structures are advancing as the demand for high-density assembly increases. We studied a fabrication process using a SoC die and a memory die for 3D-SiP (System in Package) with TSV technology. Our fabrication is comprised of two processes. One is called MEOL (Middle End of Line) for exposing and completing the TSV's in the SoC die, and the other is assembling the SoC and memory dice in a 3D stack. The TSV completion in MEOL was achieved by SoC wafer back-side processing. Because its final thickness will be a thin 50μm (typical), the SoC wafer (300 mm diameter) is temporarily attached face-down onto a carrier-wafer. Careful back-side grinding reveals the “blind vias” and fully opens them into TSV's. A passivation layer is then grown on the back of the wafer. With planarization techniques, the via metal is accessed and TSV pads are built by electro-less plating without photolithography. After the carrier-wafer is de-bonded, the thin wafer is sawed into dice. For assembling the 3D die stack, flip-chip technology by thermo-compression bonding was the method chosen. First, the SoC die with copper pillar bumps is assembled to the conventional organic substrate. Next the micro-bumps on the memory die are bonded to the TSV pads of the SoC die. Finally, the finished assembly is encapsulated and solder balls (BGA) are attached. The 3D-SiP has passed both package-level reliability and board-level reliability testing. These results show we achieved fabricating a 3D-SiP with high interconnect reliability.

Compressive behavior of small-diameter concrete-filled fiber-reinforced polymer tubes as internal reinforcements

2019 ◽  
Vol 23 (4) ◽  
pp. 713-732 ◽  
Author(s):  
Shu Fang ◽  
Li-Juan Li ◽  
Tao Jiang ◽  
Bing Fu
Keyword(s):  
Compressive Strength ◽  
High Performance ◽  
Small Diameter ◽  
Fiber Reinforced Polymer ◽  
Test Results ◽  
Fiber Reinforced ◽  
Compressive Behavior ◽  
Stress Strain ◽  
Reinforced Polymer ◽  
Polymer Tubes

Concrete infilled in a small-diameter fiber-reinforced polymer tube is strongly confined, thus having a high compressive strength and excellent deformability. Such a feature is exploited in the development of two types of high-performance hybrid members at Guangdong University of Technology, China, by incorporating small-diameter (30 to 60 mm) concrete-filled fiber-reinforced polymer tubes as internal reinforcements. Understanding the compressive behavior of small-diameter concrete-filled fiber-reinforced polymer tubes is essential to understanding the behavior of the proposed hybrid members and the development of their design approaches. This article therefore presents a systematic study on the axial compressive behavior of small-diameter concrete-filled fiber-reinforced polymer tubes with the test parameters being the thickness, diameter, and fiber type of fiber-reinforced polymer tubes and concrete strength. The test results show that the tested small-diameter concrete-filled fiber-reinforced polymer tubes have a compressive strength and an ultimate axial strain of up to 267 MPa and 10.3%, which are, respectively, about 6 and 34 times that of the corresponding unconfined specimens, demonstrating the great potential of small-diameter concrete-filled fiber-reinforced polymer tubes as internal reinforcements for use in high-performance hybrid members. The applicability of three widely accepted stress–strain models developed based on test results of fiber-reinforced polymer-confined concrete cylinders with a diameter of 150 mm or above is also examined. It is shown that the three models tend to predict a steeper second portion of stress–strain responses than the test results, revealing the need of a tailored stress–strain model for small-diameter concrete-filled fiber-reinforced polymer tubes.

Development of Plating Process for Micro Bump Formation

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000751-000777
Author(s):  
Takuma Katase ◽  
Koji Tatsumi ◽  
Tekeshi Hatta ◽  
Masayuki Ishikawa ◽  
Akihiro Masuda
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Solder Bump ◽  
Small Diameter ◽  
Lead Free ◽  
Current Status ◽  
Bump Height ◽  
Cu Pillar ◽  
Key Technologies ◽  
Connection Length

Flip chip connection has been applied to a lot of applications in order to shorten the connection length of high performance devices. Solder bumping is one of the key technologies for flip chip connections, and its quality makes a large impact on the reliability after packaging. Recently, bump size has been getting smaller to correspond to the finer connection pitch, and these types of bumps are called “micro bumps”. Electroplating is one of the methods for solder bump formation. Sn-Ag is considered as the best candidate for lead free alloy to be used for the electroplating method. Electroplating is a suitable method to form micro bumps. For micro bump connections, Cu pillar is necessary to obtain a suitable bump height. Traditionally, there have been some technical difficulties to achieve smooth morphology on “micro bump” surfaces due to its small diameter and/or high aspect ratio. Lately, we succeeded in developing a new Sn-Ag plating process for micro bump formation by optimizing the plating process. We also successfully developed our Cu plating process for Cu pillar application with a high plating rate more than 10 ASD condition. Our Cu plating process is available to obtain various surface shapes of Cu pillar such as flat, dome, and concave. In this study, we established our plating process with Cu pillar + Sn-Ag solder cap. We will review our current status and features of our plating chemical for micro bump formation.

Prospects for convergent beam electron diffraction with a 200kV cold field-emission transmission electron microscope

1991 ◽  
Vol 49 ◽  
pp. 466-467
Author(s):  
J W Steeds ◽  
R Vincent
Keyword(s):  
Field Emission ◽  
High Performance ◽  
Small Diameter ◽  
Convergent Beam Electron Diffraction ◽  
Zone Axis ◽  
Medium Voltage ◽  
Transmission Electron ◽  
Good Crystallinity ◽  
Special Modification ◽  
Convergent Beam

We review the analytical powers which will become more widely available as medium voltage (200-300kV) TEMs with facilities for CBED on a nanometre scale come onto the market. Of course, high performance cold field emission STEMs have now been in operation for about twenty years, but it is only in relatively few laboratories that special modification has permitted the performance of CBED experiments. Most notable amongst these pioneering projects is the work in Arizona by Cowley and Spence and, more recently, that in Cambridge by Rodenburg and McMullan.There are a large number of potential advantages of a high intensity, small diameter, focussed probe. We discuss first the advantages for probes larger than the projected unit cell of the crystal under investigation. In this situation we are able to perform CBED on local regions of good crystallinity. Zone axis patterns often contain information which is very sensitive to thickness changes as small as 5nm. In conventional CBED, with a lOnm source, it is very likely that the information will be degraded by thickness averaging within the illuminated area.

Investigating the use of small-diameter softwood as guardrail posts: static test results

2007 ◽  
Author(s):  
David E. Kretschmann ◽  
Ron Faller ◽  
Jason Hascall ◽  
John Reid ◽  
Dean Sicking ◽  
...  
Keyword(s):  
Small Diameter ◽  
Test Results ◽  
Static Test

Thin-Die Flip Chip Physical-FA Process Flow

2002 ◽  
Author(s):  
Andrew J. Komrowski ◽  
N. S. Somcio ◽  
Daniel J. D. Sullivan ◽  
Charles R. Silvis ◽  
Luis Curiel ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Fault Isolation ◽  
Preparation Methods ◽  
Chip Technology ◽  
Isolation Test ◽  
Sample Preparation Methods

Abstract The use of flip chip technology inside component packaging, so called flip chip in package (FCIP), is an increasingly common package type in the semiconductor industry because of high pin-counts, performance and reliability. Sample preparation methods and flows which enable physical failure analysis (PFA) of FCIP are thus in demand to characterize defects in die with these package types. As interconnect metallization schemes become more dense and complex, access to the backside silicon of a functional device also becomes important for fault isolation test purposes. To address these requirements, a detailed PFA flow is described which chronicles the sample preparation methods necessary to isolate a physical defect in the die of an organic-substrate FCIP.

Electron Beam Absorbed Current as a Means of Locating Metal Defectivity on 45nm SOI Technology

2010 ◽  
Author(s):  
K. Dickson ◽  
G. Lange ◽  
K. Erington ◽  
J. Ybarra
Keyword(s):  
Electron Beam ◽  
Flip Chip ◽  
Back Side ◽  
Soi Technology

Abstract This paper describes the use of Electron Beam Absorbed Current (EBAC) mapping performed from the back side of the device as a means of locating metallization defects on flip chip 45nm SOI technology.

Manufacturing In-Line Whole Wafer Focused Ion Beam (FIB) Memory Address Descramble Verification

2008 ◽  
Author(s):  
Steven B. Herschbein ◽  
Hyoung H. Kang ◽  
Scott L. Jansen ◽  
Andrew S. Dalton
Keyword(s):  
Flip Chip ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Random Access ◽  
Cell Counting ◽  
Test Results ◽  
Laboratory Procedure ◽  
Memory Array ◽  
Dual Beam ◽  
Process Level

Abstract Test engineers and failure analyst familiar with random access memory arrays have probably encountered the frustration of dealing with address descrambling. The resulting nonsequential internal bit cell counting scheme often means that the location of the failing cell under investigation is nowhere near where it is expected to be. A logical to physical algorithm for decoding the standard library block might have been provided with the design, but is it still correct now that the array has been halved and inverted to fit the available space in a new processor chip? Off-line labs have traditionally been tasked with array layout verification. In the past, hard and soft failures could be induced on the frontside of finished product, then bitmapped to see if the sites were in agreement. As density tightened, flip-chip FIB techniques to induce a pattern of hard fails on packaged devices came into practice. While the backside FIB edit method is effective, it is complex and expensive. The installation of an in-line Dual Beam FIB created new opportunities to move FA tasks out of the lab and into the FAB. Using a new edit procedure, selected wafers have an extensive pattern of defects 'written' directly into the memory array at an early process level. Bitmapping of the RAM blocks upon wafer completion is then used to verify correlation between the physical damaged cells and the logical sites called out in the test results. This early feedback in-line methodology has worked so well that it has almost entirely displaced the complex laboratory procedure of backside FIB memory array descramble verification.

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