scholarly journals Impact of Mole Fraction Variation on Nanoscale SiGe Hybrid FinFET on Insulator

2019 ◽  
Vol 8 (12S2) ◽  
pp. 61-66
Keyword(s):  
Band Gap ◽  
Mole Fraction ◽  
High Performance ◽  
Device Simulation ◽  
Channel Length ◽  
Gate Length ◽  
Electrical Characteristics ◽  
Simulation Results ◽  
High Performance Application ◽  
Device Modelling

This work investigates the performance of SiGe Hybrid JunctionLess FinFET (HJLFinFET) on insulator with different mole fraction x. The band gap difference for different mole fractions are explored. Impact of electrical characteristics and SCE of HJLFinFET are analyzed with fin width 10nm and varying gate length from 5nm-40nm for different mole fraction. Synopsys Sentaurus TCAD tool(sprocess and sdevice) are used in Device modelling and device simulation. Simulation results shows improvement in On current, DIBL and SS. For high performance application SiGe with mole fraction less than 0.3 at channel length less than 10nm are suitable because of the bandgap value is similar to silicon.

High Performance HFET Devices on Sapphire and SiC: Passivation with AlN

2002 ◽  
Vol 743 ◽  
Author(s):  
Jennifer A. Bardwell ◽  
Ying Liu ◽  
James B. Webb ◽  
Haipeng Tang ◽  
Stephen J. Rolfe ◽  
...  
Keyword(s):  
High Performance ◽  
Electron Gas ◽  
Drain Current ◽  
Gate Length ◽  
Electrical Characteristics ◽  
Dimensional Electron ◽  
Frequency Responses ◽  
Current Collapse ◽  
Dimensional Electron Gas ◽  
Load Pull

ABSTRACTAlGaN/GaN two dimensional electron gas (2DEG) heterostructures were grown by ammonia-MBE on sapphire and SiC substrates. Devices fabricated from these optimized HFET layers, with optically defined gates showed excellent characteristics, e.g. a maximum drain current density of 1.3 A/mm, maximum transconductance of 220 mS/mm, fT of 15.6 GHz and fMAX of 58.1 GHz was measured for devices with 0.9 μm gate length and 40 μm gate width. Shorter gate length devices exhibited higher frequency responses: fT of 68 GHz and fMAX of 125 GHz for 0.25 μm gate length and fT of 103 GHz and fMAX of 170 GHz for 0.15 μm gate length. However, these devices showed “current collapse” when subjected to load pull measurements. Current collapse was also observed in sequentially repeated DC measurements in the dark, both on sapphire and SiC substrates, although the degree of collapse varied greatly from one wafer to another. One method of reducing the current collapse was to apply a thin (100 - 6000 Å) magnetron sputtered AlN passivation layer (over the gates) or a 500 Å layer under the gates so that MISFET devices were obtained. The electrical characteristics of the passivated and unpassivated devices are discussed.

scholarly journals Device Simulation of The GeSe Homojunction And vdW GeSe/GeTe Heterojunction TFETs For High-Performance Application

2021 ◽  
Author(s):  
Qida Wang ◽  
Peipei Xu ◽  
Hong Li ◽  
Fengbin Liu ◽  
Shuai Sun ◽  
...  
Keyword(s):  
Ab Initio ◽  
Quantum Transport ◽  
Delay Time ◽  
High Performance ◽  
Device Simulation ◽  
Promising Method ◽  
Tunneling Barrier ◽  
High Performance Application ◽  
Power Delay Product ◽  
Source Use

Abstract Compared with a 2D homogeneous channel, the introduction of a 2D/2D homojunction or heterojunction is a promising method to promote the performance of a TFET mainly by controlling the tunneling barrier. We simulate the 10-nm-Lg double-gated GeSe homojunction TFETs and vdW GeSe/GeTe heterojunction TFETs using the ab initio quantum transport calculations. Two constructions are considered for both the homojunction and heterojunction TFETs by placing the BL GeSe and vdW GeSe/GeTe heterojunction as the source or drain while the channel and the remaining drain or source use ML GeSe. The on-state current (Ion) of the optimal n-type BL-ML GeSe source homojunction TFET and the optimal p-type vdW GeSe/GeTe drain heterojunction TFET are 2320 and 2387 μA μm-1, respectively, which are 50% and 64% larger than Ion of the ML GeSe homogeneous TFET. Inspiringly, the device performances (Ion, intrinsic delay time τ, and power delay product PDP) of both the optimal n-type GeSe homojunction and p-type vdW GeSe/GeTe heterojunction TFETs meet the requirement of the International Roadmap for Device and Systems high-performance device for the year of 2034 (2020 version).

Gate Technology Issues for Silicon Mos Nanotransistors

1999 ◽  
Vol 584 ◽  
Author(s):  
D. M Tennant ◽  
G. L. Timp ◽  
L. E. Ocola ◽  
M. Green ◽  
T. Sorsch ◽  
...  
Keyword(s):  
High Performance ◽  
Gate Dielectric ◽  
Ring Structure ◽  
Channel Length ◽  
Low Energy ◽  
Gate Length ◽  
Direct Write ◽  
Mos Transistors ◽  
Processing Elements ◽  
Effective Channel

AbstractThis article reviews technology issues in scaling conventional planar transistors to a physical gate length of 30nm that are expected to produce an effective channel length of 10 nm. Gate fabrication features direct write e-beam lithography to form a ring structure capable of exploring the practical limits of gate processing while requiring only a single level of lithography. Other processing elements include ultra-thin gate dielectric formation (∼ 0.6nm); highly selective transformer coupled plasma (TCP) etching; and low energy ion implantation. DC electrical results obtained for high performance n-MOS and p-MOS type nanotransistors made using this process are discussed as are simulations of sub-threshold currents for n-MOS transistors with physical gate lengths down to 26nm

scholarly journals Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Grand Challenge ◽  
Gate Length ◽  
Delay Performance ◽  
Effect Transistor

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

High-Performance Vertical Organic Transistors of Sub-5 nm Channel Length

Nano Letters ◽  
2021 ◽  
Author(s):  
Jakob Lenz ◽  
Anna Monika Seiler ◽  
Fabian Rudolf Geisenhof ◽  
Felix Winterer ◽  
Kenji Watanabe ◽  
...  
Keyword(s):  
High Performance ◽  
Channel Length ◽  
Organic Transistors

scholarly journals 3D Simulation-Based Acoustic Wave Resonator Analysis and Validation Using Novel Finite Element Method Software

Sensors ◽  
2021 ◽  
Vol 21 (8) ◽  
pp. 2715
Author(s):  
Ruth Yadira Vidana Morales ◽  
Susana Ortega Cisneros ◽  
Jose Rodrigo Camacho Perez ◽  
Federico Sandoval Ibarra ◽  
Ricardo Casas Carrillo
Keyword(s):  
Finite Element ◽  
High Performance ◽  
Cloud Services ◽  
3D Simulation ◽  
3D Simulations ◽  
Acoustic Resonators ◽  
Analysis And Design ◽  
Wave Resonator ◽  
Film Bulk ◽  
Simulation Results

This work illustrates the analysis of Film Bulk Acoustic Resonators (FBAR) using 3D Finite Element (FEM) simulations with the software OnScale in order to predict and improve resonator performance and quality before manufacturing. This kind of analysis minimizes manufacturing cycles by reducing design time with 3D simulations running on High-Performance Computing (HPC) cloud services. It also enables the identification of manufacturing effects on device performance. The simulation results are compared and validated with a manufactured FBAR device, previously reported, to further highlight the usefulness and advantages of the 3D simulations-based design process. In the 3D simulation results, some analysis challenges, like boundary condition definitions, mesh tuning, loss source tracing, and device quality estimations, were studied. Hence, it is possible to highlight that modern FEM solvers, like OnScale enable unprecedented FBAR analysis and design optimization.

Electronic structure engineering of tin telluride through co-doping of bismuth and indium for high performance thermoelectrics: a synergistic effect leading to a record high room temperature ZT in tin telluride

2019 ◽  
Vol 7 (16) ◽  
pp. 4817-4821 ◽  
Author(s):  
U. Sandhya Shenoy ◽  
D. Krishna Bhat
Keyword(s):  
Electronic Structure ◽  
Synergistic Effect ◽  
Band Gap ◽  
High Performance ◽  
Room Temperature ◽  
Band Offset ◽  
Valence Band Offset ◽  
Co Doping ◽  
Tin Telluride ◽  
Structure Engineering

Resonance states due to Bi and In co-doping, band gap enlargement, and a reduced valence-band offset in SnTe lead to a record high room-temperature ZT.

scholarly journals Optimization of Dynamic Task Location within a Manipulator’s Workspace for the Utilization of the Minimum Required Joint Torques

Electronics ◽  
2021 ◽  
Vol 10 (3) ◽  
pp. 288
Author(s):  
Adam Wolniakowski ◽  
Charalampos Valsamos ◽  
Kanstantsin Miatliuk ◽  
Vassilis Moulianitis ◽  
Nikos Aspragathos
Keyword(s):  
High Performance ◽  
Human Robot Interaction ◽  
Optimal Position ◽  
End Effector ◽  
Joint Torques ◽  
Dynamic Task ◽  
Arbitrary Position ◽  
Simulation Results ◽  
Set Up ◽  
Task Placement

The determination of the optimal position of a robotic task within a manipulator’s workspace is crucial for the manipulator to achieve high performance regarding selected aspects of its operation. In this paper, a method for determining the optimal task placement for a serial manipulator is presented, so that the required joint torques are minimized. The task considered comprises the exercise of a given force in a given direction along a 3D path followed by the end effector. Given that many such tasks are usually conducted by human workers and as such the utilized trajectories are quite complex to model, a Human Robot Interaction (HRI) approach was chosen to define the task, where the robot is taught the task trajectory by a human operator. Furthermore, the presented method considers the singular free paths of the manipulator’s end-effector motion in the configuration space. Simulation results are utilized to set up a physical execution of the task in the optimal derived position within a UR-3 manipulator’s workspace. For reference the task is also placed at an arbitrary “bad” location in order to validate the simulation results. Experimental results verify that the positioning of the task at the optimal location derived by the presented method allows for the task execution with minimum joint torques as opposed to the arbitrary position.

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