An on-chip testbed that emulates runtime traffic and reduces design verification time for FPGA designs

2008 ◽  
Author(s):  
Wayne Chen ◽  
Lesley Shannon
Keyword(s):  
Design Verification ◽  
Verification Time ◽  
On Chip

Advanced sub 0.13µm Cu Devices – Failure Analysis and Circuit Edit With Improved FIB Chemical Processes and Beam Characteristics

2002 ◽  
Author(s):  
J. David Casey ◽  
Thomas J. Gannon ◽  
Alex Krechmer ◽  
David Monforte ◽  
Nicholas Antoniou ◽  
...  
Keyword(s):  
Failure Analysis ◽  
High Speed ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Chemical Processes ◽  
Design Verification ◽  
End Point Detection ◽  
On Chip ◽  
Point Detection ◽  
Low K

Abstract Advances in FIB (focused ion beam) chemical processes and in the Ga (gallium) beam profile are discussed; these advances are necessary for the successful failure analysis, circuit edit and design verification of advanced, sub-0.13µm Cu devices. Included in this article are: a novel FIB method (CopperRx) for smoothly milling thick, large grained Cu lines; H2O and O2 processes for cleanly cutting thin, smaller grained Cu lines, thereby forming electrically open interconnects; a XeF2 GAE (gas assisted etching) process for etching low k, CVD dielectrics such as F and C doped SiO2; H2O and XeF2 GAE processes for etching low k, spin-on, organic dielectrics such as SiLK; a recently developed recipe for the deposition of SiO2 based material with intermediate resistivity (106 µohm·cm) which is useful in the design verification of frequency sensitive, high speed analog and SOC (system on chip) circuits; an improved, more Gaussian Ga beam with less current density in the beam tails (VisION column) which provides higher resolution, real time images needed for end-point detection on sub 0.13µm features during milling.

Low-Power Code Memory Integrity Verification Using Background Cyclic Redundancy Check Calculator Based on Binary Code Inversion Method

2016 ◽  
Vol 25 (07) ◽  
pp. 1650068
Author(s):  
Daejin Park
Keyword(s):  
Low Power ◽  
Flash Memory ◽  
Binary Code ◽  
Inversion Method ◽  
Cyclic Redundancy Check ◽  
Integrity Verification ◽  
Verification Time ◽  
Average Current ◽  
On Chip ◽  
Background Mode

The integrity verification of on-chip flash memory data as code memory is becoming important in microcontroller-based applications such as automotive systems. On-the-fly memory fail-detection requires a fast detection method in the seamless background mode without any interruption of CPU operation and low-power flash access hardware to provide safety-conscious execution of the user-programmed firmware during system operations. In this paper, newly-designed read-path architecture based on the binary inversion techniques is proposed for on-chip flash-embedded microcontrollers. The proposed binary inversion method also enables fail-safe, low-power memory access with zero hardware overhead by embedding the scramble flags on the cyclic redundancy check (CRC) protection code. Time-multiplexed CRC calculation for bit-inversion binary code is automatically executed with the silent background mode during CPU idle time without any CPU wait cost. The implementation result shows that the de-inversion procedure could be achieved with just an additional 1,024 bits CRC data in the case of 64 sectors for 4 KB flash memory by reducing 75% of the area of the previous work. The code memory integrity verification time in the seamless background mode is about 30% of the conventional foreground method. The total average current during the code execution for DhrystoneTM benchmark uses just 15% of the basement.

Industrial Applications of Emulation Techniques for the Early Evaluation of Secure Low-Power Embedded Systems

2014 ◽  
pp. 328-346
Author(s):  
Norbert Druml ◽  
Manuel Menghin ◽  
Christian Steger ◽  
Armin Krieg ◽  
Andreas Genser ◽  
...  
Keyword(s):  
Embedded Systems ◽  
Low Power ◽  
Network Models ◽  
Industrial Applications ◽  
Early Evaluation ◽  
Traditional System ◽  
Verification Time ◽  
On Chip ◽  
High Level ◽  
Verification Methodology

Embedded systems that follow a secure and low-power design methodology are, besides keeping strict design constraints, heavily dependent on comprehensive test and verification procedures. The large set of possible test vectors and the increasing density of System-on-Chip designs call for the introduction of hardware-accelerated techniques to solve the verification time problem. As already described earlier, emulation-based methodologies based on FPGA evaluation platforms prove capable of providing a solution compared to traditional system simulation. This chapter gives an introduction into a multi-disciplinary emulation-based design evaluation and verification methodology that is based on various techniques that have been presented in chapter 5. Test and verification capabilities are enhanced by the augmentation of this approach using model-based analysis units: gate-level-based power consumption models, power supply network models, event-based performance monitors, and high-level fault modes. The feasible usage of this verification methodology in the field of contactlessly powered smart cards is finally demonstrated using several industrial case studies.

A Novel Prototyping and Evaluation Framework for NoC-Based MPSoC

2013 ◽  
Vol 4 (3) ◽  
pp. 1-24 ◽  
Author(s):  
K. Tatas ◽  
K. Siozios ◽  
A. Bartzas ◽  
C. Kyriacou ◽  
D. Soudris
Keyword(s):  
Rapid Prototyping ◽  
Automated Design ◽  
Network On Chip ◽  
Register Transfer Level ◽  
Evaluation Framework ◽  
Design Flow ◽  
Verification Time ◽  
Cost Simulation ◽  
On Chip ◽  
High Level

This paper presents a framework for high-level exploration, Register Transfer-Level (RTL) design and rapid prototyping of Network-on-Chip (NoC) architectures. From the high-level exploration, a selected NoC topology is derived, which is then implemented in RTL using an automated design flow. Furthermore, for verification purposes, appropriate self-checking testbenches for the verification of the RTL and architecture files for the semi-automatic implementation of the system in Xilinx EDK are also generated, significantly reducing design and verification time, and therefore Non-Recurring Engineering (NRE) cost. Simulation and FPGA implementation results are given for four case studies multimedia applications, proving the validity of the proposed approach.

scholarly journals Viable System Verilog Assertions(SVA) Praxis in AMBA AHB-Lite Protocol Design

2020 ◽  
Vol 9 (6) ◽  
pp. 30-33
Keyword(s):  
Design Process ◽  
Integrated Circuit ◽  
Design Methodology ◽  
Protocol Design ◽  
Design Verification ◽  
Ic Design ◽  
Intelligent Software ◽  
On Chip ◽  
Viable System ◽  
Eda Tools

Digital integrated circuit(ic design entanglement has been far reaching since the demonstration by kil by in 1958.in this day and age system on chip(soc) design verification accommodate billion , more specifically trillion transistors designs came into existence due to artificial intelligence(ai) designs. The expertise designers tried to ramp up design process by using effective eda tools , still the time wheel move in recursive process. In order to accelerate time wheel of design process specified design methodology needed for every design. The overview of various design methodologies followed in the market now a days. Emulation performance by using veloce platform in bfm mode on ahb lite transmissions. Simulation by using software eda tools is slow going on wheel of design when we go for higher abstraction. Accelerated simulation and emulation using hardware is costly in contrast with software simulation. Prototyping is expedient. Formal verification and intelligent software simulations are frail. The possibility of selection between various hardware engines become ravelled. It develop into perspicuous only amalgamation of engines will assist design verification teams to be triumphant. In this design combination of hardware accelerated simulator as a combination of emulator used to accelerate time wheel by using arm amba ahb lite protocol as a design.

scholarly journals Implementation of VIP for bus interface logic of 32-bit processor using System Verilog

2019 ◽  
pp. 205-211
Keyword(s):  
Intellectual Property ◽  
Functional Verification ◽  
Test Cases ◽  
Design Verification ◽  
Code Coverage ◽  
Verification Time ◽  
Bus Architecture

A verification environment to verify an ARM-based SoC is proposed in this work. This work introduces the design of a Verification Intellectual Property (VIP) of Advanced Microcontroller Bus Architecture (AMBA). AMBA protocols are today the best standards for 32-bit processor because they are well documented and can be used without royalties. The VIP provides Coverage Driven Verification (CDV) which significantly reduces the design verification time. The code coverage verification of the AHB bus master, Icache controller, Dcache controller and APB peripherals such as APB bridge, timer, UART, and ACE is done in this work. The test cases done for the APB peripherals are ACE with the mil_std_protocol, Timers for generation of interrupt and watchdog reset, UART for transmitting and receive messages, and interrupt registers for Reading and Write. The functional verification of AMBA is carried out using the Mentor Graphics Questasim tool with the system Verilog language

Gut microbiome a promising target for management of respiratory diseases

2020 ◽  
Vol 477 (14) ◽  
pp. 2679-2696
Author(s):  
Riddhi Trivedi ◽  
Kalyani Barve
Keyword(s):  
Respiratory Diseases ◽  
New Technology ◽  
Bacterial Flora ◽  
Systemic Circulation ◽  
The Body ◽  
Lung Pathology ◽  
Promising Target ◽  
Current Therapies ◽  
Intestinal Microbial Flora ◽  
On Chip

The intestinal microbial flora has risen to be one of the important etiological factors in the development of diseases like colorectal cancer, obesity, diabetes, inflammatory bowel disease, anxiety and Parkinson's. The emergence of the association between bacterial flora and lungs led to the discovery of the gut–lung axis. Dysbiosis of several species of colonic bacteria such as Firmicutes and Bacteroidetes and transfer of these bacteria from gut to lungs via lymphatic and systemic circulation are associated with several respiratory diseases such as lung cancer, asthma, tuberculosis, cystic fibrosis, etc. Current therapies for dysbiosis include use of probiotics, prebiotics and synbiotics to restore the balance between various species of beneficial bacteria. Various approaches like nanotechnology and microencapsulation have been explored to increase the permeability and viability of probiotics in the body. The need of the day is comprehensive study of mechanisms behind dysbiosis, translocation of microbiota from gut to lung through various channels and new technology for evaluating treatment to correct this dysbiosis which in turn can be used to manage various respiratory diseases. Microfluidics and organ on chip model are emerging technologies that can satisfy these needs. This review gives an overview of colonic commensals in lung pathology and novel systems that help in alleviating symptoms of lung diseases. We have also hypothesized new models to help in understanding bacterial pathways involved in the gut–lung axis as well as act as a futuristic approach in finding treatment of respiratory diseases caused by dysbiosis.

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