DC noise margin and failure analysis of proposed low swing voltage SRAM cell for high speed CMOS circuits

2013 ◽  
Author(s):  
Prashant Upadhyay ◽  
R. Kar ◽  
D. Mandal ◽  
S. P. Ghoshal
Keyword(s):  
Failure Analysis ◽  
High Speed ◽  
Cmos Circuits ◽  
Noise Margin ◽  
Sram Cell

Design and Analysis of SRAM Cell using Negative Bit-Line Write Assist Technique and Separate Read Port for High-Speed Applications

2021 ◽  
pp. 2150270
Author(s):  
Jitendra Kumar Mishra ◽  
Lakshmi Likhitha Mankali ◽  
Kavindra Kandpal ◽  
Prasanna Kumar Misra ◽  
Manish Goswami
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Random Access ◽  
Random Access Memory ◽  
Access Memory ◽  
Static Noise Margin ◽  
Semiconductor Memory ◽  
Noise Margin ◽  
Sram Cell ◽  
Static Noise

The present day electronic gadgets have semiconductor memory devices to store data. The static random access memory (SRAM) is a volatile memory, often preferred over dynamic random access memory (DRAM) due to higher speed and lower power dissipation. However, at scaling down of technology node, the leakage current in SRAM often increases and degrades its performance. To address this, the voltage scaling is preferred which subsequently affects the stability and delay of SRAM. This paper therefore presents a negative bit-line (NBL) write assist circuit which is used for enhancing the write ability while a separate (isolated) read buffer circuit is used for improving the read stability. In addition to this, the proposed design uses a tail (stack) transistor to decrease the overall static power dissipation and also to maintain the hold stability. The comparison of the proposed design has been done with state-of-the-art work in terms of write static noise margin (WSNM), write delay, read static noise margin (RSNM) and other parameters. It has been observed that there is an improvement of 48%, 11%, 19% and 32.4% in WSNM while reduction of 33%, 39%, 48% and 22% in write delay as compared to the conventional 6T SRAM cell, NBL, [Formula: see text] collapse and 9T UV SRAM, respectively.

A Read-Static-Noise-Margin-Free SRAM Cell for Low-VDD and High-Speed Applications

2006 ◽  
Vol 41 (1) ◽  
pp. 113-121 ◽  
Author(s):  
K. Takeda ◽  
Y. Hagihara ◽  
Y. Aimoto ◽  
M. Nomura ◽  
Y. Nakazawa ◽  
...  
Keyword(s):  
High Speed ◽  
Static Noise Margin ◽  
Noise Margin ◽  
Sram Cell ◽  
Static Noise

The SRAM Soft Failure Analysis with SNM & TR Characterization by Nanoprobing in Sub 45nm

2009 ◽  
Author(s):  
Jakyung Hong ◽  
S.J. Cho ◽  
Y.W. Han ◽  
H.S. Choi ◽  
T.E. Kim ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Metal Layer ◽  
Noise Margin ◽  
Soft Failure ◽  
Sram Cell ◽  
Cell Stability ◽  
The Stability ◽  
Static Noise

Abstract This paper presents the process of measuring static noise margin (SNM), write noise margin (WNM) with 6 pin nanoprober, and characterization and analysis of SRAM cell stability through case studies of 45nm devices SRAM soft failures. It highlights that the local mismatch in the bit cell caused by slight variations in the transistor characteristics, such as Vth shift and Idsat, off variation, also can easily induce a soft failure. The analysis of the SNM TR characteristic is successfully demonstrated through the case study of 45nm SRAM devices. The chapter explains SNM measurement in the metal layer and transistor measurements in the CA layer. Measuring the SNM TR's characteristics is an important methodology in understanding the stability of each bit cell and failure mechanism depending on voltage, defects, and other factors. The next generation of nanoprobing analysis can be expanded.

A 3.1 GB/s, 8 Kb, ZERO PRECHARGE, PIPELINED, HIGHLY STABLE 2-PORT 8T SRAM DESIGN IN 65 nm

2013 ◽  
Vol 22 (08) ◽  
pp. 1350069 ◽  
Author(s):  
ABHIJIT SIL ◽  
KRISHNA PRASAD BALUSU ◽  
CHANDRA SEKHAR GURRAM ◽  
MAGDY BAYOUMI
Keyword(s):  
High Speed ◽  
Data Transfer ◽  
Supply Voltage ◽  
Access Time ◽  
Pipeline Architecture ◽  
Noise Margin ◽  
Sram Cell ◽  
Sram Design ◽  
Cell Current ◽  
Stability Issues

As the supply voltage is reducing with feature size, SRAM cell design is going through severe stability issues. The issue becomes worse due to increased variability in below sub-100 nm technology. In this paper, we present a highly stable 2-port 8T SRAM cell for high speed application in 65 nm technology. The proposed design provides high stability under simultaneous read/write disturbed access without reducing the I cell . The cell characteristic is extensively examined under random variation. The dynamic read noise margin is improved by 95% over conventional dual port SRAM. The zero-precharge sensing and virtual ground scheme reduce read path leakage current by 95% over conventional high precharge 2-port SRAM cell. The cell current is improved by 52% over conventional design. Finally, an 8 Kb bit-interleaved 2-stage pipelined SRAM architecture is presented using proposed cell. The 2-stage pipeline architecture provides data transfer bandwidth of 3.1 GB/s. Area-efficient 2-stage decoder layout helps to avoid pseudo read problem in unselected cells without sacrificing memory access time.

scholarly journals SRAM CELL 6T AND 8T PARAMETRIC STABILITY ANALYSIS

2021 ◽  
Vol I (I) ◽  
Author(s):  
Bharathabau K
Keyword(s):  
Stability Analysis ◽  
High Speed ◽  
Memory Cell ◽  
Parametric Stability ◽  
Static Noise Margin ◽  
Noise Margin ◽  
Sram Cell ◽  
Margin Analysis ◽  
Static Noise ◽  
Technology Advances

As technology advances, the need for SRAM cells that may be utilised in high-speed applications grows. SRAM cells' static noise margin (SNM) is one of the most important variables to consider when designing a memory cell, and it is the main predictor of SRAM cell speed. The static noise margin will have an impact on the read and write margins. When it comes to the SRAM Cell's stability, the SNM is very important. For high-speed SRAMs, read/write margin analysis is critical since it affects how much data can be read and written. The simulation was run using Mentor Graphics' IC Station, which utilised 350nm technology rather than 180nm technology.

scholarly journals Estimation of Write Noise Margin for 6t SRAM Cell in CMOS 45nm technology.

2021 ◽  
Vol 23 (05) ◽  
pp. 211-215
Author(s):  
Hima Bindu Katikala ◽  
◽  
G. Ramana Murthy ◽  
P. Raja Rajeswari ◽  
P. Sai Charan ◽  
...  
Keyword(s):  
High Speed ◽  
Random Access ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Noise Margin ◽  
Sram Cell ◽  
Scaling Process ◽  
Memory Architectures ◽  
Margin Analysis ◽  
Static Noise

For high speed application the static random access memory is mostly demandable. Such kind of device should possess additive parameters that can withstand during transistor scaling process. Their exist static noise margin (SNM) which degrades the device performance of memory architectures, majorly observed at write and read operation create write noise margin (WNM) and read noise margin (RNM). In this paper we discuss about the basic design of 6 transistor SRAM (6T SRAM) using 180nm and 45nm CMOS technology in Cadence Virtuoso with write noise margin analysis. The propagation delay, power dissipation, WNM are measured for both the technologies and observed that WNM is relatively low in 45nm.

scholarly journals A Low Power 6T-Auto Awake Mode-SRAM Design for high speed storage application

2019 ◽  
Vol 8 (9) ◽  
pp. 204-208
Keyword(s):  
Low Power ◽  
High Speed ◽  
Random Access ◽  
Digital World ◽  
Noise Margin ◽  
Sram Cell ◽  
Sram Design ◽  
Static Ram ◽  
Power Application ◽  
Reduced Power Consumption

In the digital world, Static Random Access Memory (SRAM) is one of the efficient core component for electronics design, it consumes huge amount of power and die area. In this research, the SRAM design analysis in terms of read margin, write margin and Static Noise Margin (SNM) for low power application is considered. In SRAM memory, both read and write operation affect by noise margin. So, read and write noise margins are considered as the significant challenges in designing SRAM cell. In this research, robust 6T-SRAM cell is designed to decrease the power utilization. The Auto Awake Mode is developed to control the entire 6T-SRAM cell design. The proposed 6T-SRAM- Auto Awake Mode (6T-SRAM-AAM) was implemented to reduce power utilization of understand and write down operation inside the 20 nm FinFET library. The experimental results showed the proposed 6T-SRAM-AAM design reduced power consumption of read & write operation up to 25% to 33.33% compared to existing Static RAM cells design

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