Reliability characterisation of plasma induced charging damage (PID) for MOS transistors of a silicon on insulator (SOI) process using product relevant test structures and fWLR methods

2021 ◽  
Author(s):  
Andreas Martin ◽  
Angelika Kamp ◽  
Johannes Berger
Keyword(s):  
Silicon On Insulator ◽  
Mos Transistors

Subboundary Free Submicronic Devices on Laser-Recrystallized Silicon Oninsulator

1984 ◽  
Vol 35 ◽  
Author(s):  
A.J. Auberton-Herve ◽  
J.P. Joly ◽  
J.M. Hode ◽  
J.C. Castagna
Keyword(s):  
Channel Length ◽  
Silicon On Insulator ◽  
Ring Oscillator ◽  
Mos Transistors ◽  
Seed Structure ◽  
Leakage Currents ◽  
Industrial Processing ◽  
Laser Recrystallization ◽  
Dynamic Performances ◽  
Lateral Epitaxy

ABSTRACTSeeding from bulk silicon (lateral epitaxy) has been used in Ar+ laser recrystallization to achieve subboundary free silicon on insulator areas. On these areas C.MOS devices have been performed using almost entirely the standard processing steps of a bulk micronic C-MOS technology. n -MOS transistors with channel length as small as 0.3 um have shown very small leakage currents. This is attributed especially to the lack of subboundaries. A 40 % increase in the dynamic performances in comparison with equivalent size C-MOS bulk devices has been obtained (93 ps of delay time per stage for a 101 stages ring oscillator with 0.8 μm of channel length). This is the best result presented so far on recrystallized SOI. No special requirements are needed in the lay out of the circuit with the chosen seed structure. Furthermore an industrial processing rate for the laser recrystallization processing has been achieved using an elliptical laser beam, a high scan velocity (30 cm/s) and a 100 μm line to line scan step (a 4' wafer in 4 minutes).

SiGe Heterostructures-on-Insulator Produced by Ge+-Ion Implantation and Subsequent Hydrogen Transfer

2007 ◽  
Vol 131-133 ◽  
pp. 143-148 ◽  
Author(s):  
Ida E. Tyschenko ◽  
A.G. Cherkov ◽  
M. Voelskow ◽  
V.P. Popov
Keyword(s):  
Hydrogen Transfer ◽  
Silicon Layer ◽  
Hole Mobility ◽  
Metal Oxide Semiconductor ◽  
Silicon On Insulator ◽  
Bonding Interface ◽  
Oxide Semiconductor ◽  
Mos Transistors ◽  
Germanium Nanocrystals ◽  
Germanium Layer

The properties of germanium implanted into the SiO2 layers in the vicinity of the bonding interface of silicon-on-insulator (SOI) structures are studied. It is shown that no germanium nanocrystals are formed in the buried SiO2 layer of the SOI structure as a result of annealing at the temperature of 1100° C. The implanted Ge atoms segregate at the Si/SiO2 bonding interface. In this case, Ge atoms are found at sites that are coherent with the lattice of the top silicon layer. It is found that the slope of the drain–gate characteristics of the back metal-oxide-semiconductor (MOS) transistors, prepared in the Ge+ ion implanted structures, increases. This effect is attributed to the grown hole mobility due to the contribution of an intermediate germanium layer formed at the Si/SiO2 interface.

scholarly journals Coupling effect in field Hall elements based on thin-film SOI MOS transistors

2020 ◽  
Vol 6 (4) ◽  
pp. 155-158
Author(s):  
Aleksey V. Leonov ◽  
Victor N. Murashev ◽  
Dmitry N. Ivanov ◽  
V.D. Kirilov
Keyword(s):  
Magnetic Field ◽  
Thin Film ◽  
Thin Film Transistors ◽  
High Performance ◽  
Coupling Effect ◽  
Silicon On Insulator ◽  
Mos Transistors ◽  
Magnetic Field Sensors ◽  
Magnetic Sensitivity ◽  
Hall Elements

The influence of the coupling effect on the parameters of field Hall elements based on thin-film MOS transistors has been studied. Analysis of the development of today’s microelectronics shows the necessity of developing the element base for high performance sensors based on silicon technologies. One way to significantly improve the performance of sensing elements including magnetic field sensors is the use of thin-film transistors on the basis of silicon on insulator (SOI) structures. It has been shown that field Hall sensors (FHS) may become the basis of high-performance magnetic field sensors employing the coupling effect occurring in the double gate vertical topology of these sensing elements. Electrophysical studies of FHS have been conducted for different gate bias and power supply modes. The results show that the coupling effect between the gates occurs in FHS if the thickness of the working layer between the gates is 200 nm. This effect leads to an increase in the effective carrier mobility and hence an increase in the magnetic sensitivity of the material. Thus field Hall elements based on thin-film transistors fabricated using silicon technologies provide for a substantial increase in the magnetic sensitivity of the elements and allow their application in highly reliable magnetic field sensors.

Performance Advantages of Submicron Silicon-On-Insulator Devices for ULSI

1987 ◽  
Vol 107 ◽  
Author(s):  
James C. Sturm
Keyword(s):  
Minority Carrier ◽  
Bipolar Transistors ◽  
Silicon On Insulator ◽  
Hot Electron ◽  
Saturation Current ◽  
Mos Transistors ◽  
Device Structure ◽  
Short Channel ◽  
Bulk Structures ◽  
Electron Effects

AbstractIn this paper the various performance advantages of SOI and SOS structures for submicron ULSI circuits will be described. In addition to the traditional speed and radiation-hardness advantages, there are several significant advantages of thin-film SOI compared to bulk structures for the submicron scaling of MOS transistors. These advantages include short-channel threshold voltage stability, improved sub-threshold slope, increased saturation current, and reduced hot electron effects. Both theory and data from several groups will be presented to illustrate these effects. Since these advantages all fall in areas that are critical limits to device engineering and scaling in the submicron regime, the motivation for using SOI should be even stronger as devices are scaled to smaller dimensions in the future. Consideration of SOI or SOS on the ULSI scale will require a technology capable of low defect films with a film thickness of 1000 A or less, however. The prospects for minority carrier devices such as bipolar transistors for BI-MOS will also be discussed. Both device structure (lateral vs. vertical) and material quality are issues that must be addressed.

Grain Boundary Confinement in Soi Films Using Patterned Ar Coatings and Seeded Oscillatory Growth

1983 ◽  
Vol 23 ◽  
Author(s):  
C.I. Drowley ◽  
P. Zorabedian ◽  
T.I. Kamins
Keyword(s):  
Grain Boundary ◽  
Laser Beam ◽  
Single Crystal ◽  
Grain Boundaries ◽  
Silicon On Insulator ◽  
Mos Transistors ◽  
Etch Pits ◽  
Polysilicon Films ◽  
Regular Arrays ◽  
Ar Coating

ABSTRACTRegular arrays of grain-boundary-free silicon strips several hundred microns long have been produced in a silicon-on-insulator (SOI) structure by using a patterned anti-reflection (AR) coating in combination with seeded oscillatory growth techniques. The AR coating pattern consists of a series of parallel stripes (typically 10 μm wide, separated by 10 μm spaces) starting from a seeding window. A laser beam (typically a 50 μm × 250 μm elliptical beam) is scanned perpendicular to the stripes, with the long axis of the beam parallel to the scan direction. The beam is stepped 1–2 μm between successive scans to advance the single crystal along the direction of the AR stripes. Grain boundaries are confined to the region under the AR stripes. Stereographic analysis of KOH etch pits formed in the single crystal strips has shown that the orientation of the stripes gradually rotates from (001)[110] to (013)[331] as the crystal propagates away from the seed. MOS transistors formed in the single-crystal strips have mobilities comparable to devices formed in bulk films. These mobilities are approximately 20% higher than those found in devices formed in large-grain recrystallized polysilicon films.

Offset-Gate Structures for Increased Breakdown Voltages in Silicon-On-Insulator Transistors

1984 ◽  
Vol 33 ◽  
Author(s):  
C. I. Drowley ◽  
T. I. Kamins
Keyword(s):  
Charge Density ◽  
Breakdown Voltage ◽  
Silicon On Insulator ◽  
Fixed Charge ◽  
Back Surface ◽  
Mos Transistors ◽  
Fixed Charge Density ◽  
Gate Structure ◽  
High Fields ◽  
Overlap Region

ABSTRACTAn offset-gate structure was used to fabricate p-channel MOS transistors in laser-recrystallized silicon-on-insulator (SOI) films. The breakdown voltage increased from about -18 V with a conventional gate structure to about -38 V with the offset gate and was then limited by bulk breakdown in the film, rather than by the high fields near the gate drain overlap region. Simulations indicate that breakdown voltages of about -60 V can be achieved in the structure used, provided that the back-surface fixed-charge density is limited to 1×10″ cm−2.

Carrier Accumulation in Silicon-On-Insulator Structures Containing Ge Nanocrystals in the Burried SiO2 Layer

2005 ◽  
Vol 108-109 ◽  
pp. 77-82
Author(s):  
Ida E. Tyschenko ◽  
A.A. Frantsuzov ◽  
O.V. Naumova ◽  
B.I. Fomin ◽  
D.V. Nikolaev ◽  
...  
Keyword(s):  
Physical Properties ◽  
Positive Charge ◽  
Silicon Layer ◽  
Silicon On Insulator ◽  
Electron Trapping ◽  
Mos Transistors ◽  
Electrical Field ◽  
Excess Positive Charge ◽  
Mos Structures ◽  
Ge Nanocrystals

Electro-physical properties of metal-oxide-silicon (MOS) structures and MOS transistors, prepared in the top silicon layer of silicon-on-insulator (SOI) structures containing Ge nanocrystals in the buried SiO2 layers, have been studied. It was obtained that carrier accumulation in MOS structures depend on the direction of built-in electrical field in MOS structures. Accumulation of the excess negative charges in the case of p-channel transistors is associated with electron trapping on Ge nanocrystals synthesized in the buried dielectric. In the case of n-channel transistor, positive charge related to the Si/SiO2 interface or to the charged oxide is accumulated. The Ge atoms diffused to the SiO2/Si interface can stimulate the formation of the excess positive charge.

Sign in / Sign up

Export Citation Format

Share Document