Influences of sandwiched structure trench and temperature on the latch-up reliability of LIGBT on thick SOI substrate

2017 ◽  
Author(s):  
Chunwei Zhang ◽  
Yang Li ◽  
Xiaoqian Fu ◽  
Zhiming Li
Keyword(s):  
Sandwiched Structure ◽  
Latch Up

Latch-Up Induced Slit Voiding in Aluminum Metal Lines

1999 ◽  
Author(s):  
Chunyu Zhang ◽  
Lakshmi Vedula ◽  
Shekhar Khandekar
Keyword(s):  
High Temperature ◽  
Line Width ◽  
Fold Increase ◽  
Metal Line ◽  
Operating Life ◽  
Mixed Signal ◽  
Aluminum Metal ◽  
Temperature Operating ◽  
Latch Up

Abstract Latch-up induced during High Temperature Operating Life (HTOL) test of a mixed signal device fabricated with 1.0 μm CMOS, double poly, double metal process caused failures due to an open in aluminum metal line. Metal lines revealed wedge voids of about 50% of the line width. Triggering of latch up mechanism during the HTOL test resulted in a several fold increase of current flowing through the ground metal line. This increase in current resulted in the growth of the wedge voids leading to failures due to open metal lines.

A Silicon Debugging Methodology on Customer Prototype for Wafer Foundries

2012 ◽  
Author(s):  
Mai Zhihong ◽  
Ng Tsu Hau ◽  
Dawood M. Khalid ◽  
Tan Pik Kee ◽  
Jeffrey Lam
Keyword(s):  
Case Studies ◽  
Semiconductor Industry ◽  
Full Information ◽  
Limited Information ◽  
Ip Protection ◽  
First Case ◽  
Silicon Debugging ◽  
Failure Location ◽  
Device Chip ◽  
Latch Up

Abstract IP protection is of major importance for a semiconductor company and only limited information is made available for device debugging for the product outsourced to a foundry. In order to position ourselves better in the ever competitive semiconductor industry, with the consideration of IP protection, we have to provide the customers with the Si debugging capability and device/chip verification services in foundry. This paper explores the Si debugging methodology and technique in a foundry. Two case studies are presented and discussed. The first case illustrates the isolation of the failure location by InGaAs microscopy, upon which the failure was identified to be caused by a latch-up issue. In the second case, due to confidentiality considerations from the customer, full information could not be provided to the foundry for silicon debugging. The paper illustrates the ability to effectively debug a failure despite being constrained by limited information from the customer.

РАДИАЦИОННО СТОЙКОЕ КМОП СТАТИЧЕСКОЕ ОЗУ 16 МБИТ 1657РУ2У

2020 ◽  
Vol 96 (3s) ◽  
pp. 169-174
Author(s):  
Ю.М. Герасимов ◽  
Н.Г. Григорьев ◽  
А.В. Кобыляцкий ◽  
Я.Я. Петричкович
Keyword(s):  
Total Dose ◽  
Heavy Particles ◽  
Topological Features ◽  
Radiation Hardened ◽  
Latch Up

Рассматриваются архитектурные, схемотехнические и конструктивно-топологические особенности асинхронного радиационно стойкого ОЗУ 1657РУ2У емкостью 16 Мбит с организацией (1Мx16)/(2Mx8), изготавливаемого по коммерческой КМОП-технологии объемного кремния уровня 130 нм. СБИС ОЗУ нечувствительна к эффекту «защелкивания», имеет повышенные дозовую стойкость и сбоеустойчивость при воздействии отдельных ядерных частиц (ОЯЧ), протонов и нейтронов (ТЧ). The paper highlights architectural, schematic and topological features of the radiation hardened 16 Mbit CMOS SRAM with configurable organization 1Mx16/2Mx8, which is immune to latch-up and with improved total dose and heavy particles tolerance.

scholarly journals Multi-Level Switching of Al-Doped HfO2 RRAM with a Single Voltage Amplitude Set Pulse

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 731
Author(s):  
Jinfu Lin ◽  
Shulong Wang ◽  
Hongxia Liu
Keyword(s):  
Random Access ◽  
Resistive Random Access Memory ◽  
Programming Algorithm ◽  
Voltage Amplitude ◽  
Strength Change ◽  
Value Range ◽  
Multi Level ◽  
Conductance States ◽  
Switching Characteristics ◽  
Sandwiched Structure

In this paper, the resistive switching characteristics in a Ti/HfO2: Al/Pt sandwiched structure are investigated for gradual conductance tuning inherent functions. The variation in conductance of the device under different amplitudes and voltage pulse widths is studied. At the same time, it was found that the variation in switching parameters in resistive random-access memory (RRAM) under impulse response is impacted by the initial conductance states. The device was brought to a preset resistance value range by energizing a single voltage amplitude pulse with a different number of periodicities. This is an efficient and simple programming algorithm to simulate the strength change observed in biological synapses. It exhibited an on/off of about 100, an endurance of over 500 cycles, and a lifetime (at 85 °C) of around 105 s. This multi-level switching two-terminal device can be used for neuromorphic applications to simulate the gradual potentiation (increasing conductance) and inhibition (decreasing conductance) in an artificial synapse.

Emitter injection control in LVTSCR for latch-up free ESD protection

2003 ◽  
Author(s):  
V. Vashchenko ◽  
A. Concannon ◽  
M. Ter Beek ◽  
P. Hopper
Keyword(s):  
Esd Protection ◽  
Injection Control ◽  
Latch Up

Photoelectric Laser Stimulation applied to Latch-Up phenomenon and localization of parasitic transistors in an industrial failure analysis laboratory

2011 ◽  
Vol 51 (9-11) ◽  
pp. 1658-1661 ◽  
Author(s):  
R. Llido ◽  
J. Gomez ◽  
V. Goubier ◽  
N. Froidevaux ◽  
L. Dufayard ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Laser Stimulation ◽  
Analysis Laboratory ◽  
Latch Up

Effects of the interaction of neighboring structures on the latch-up behavior of CMOS ICs

1991 ◽  
Vol 38 (8) ◽  
pp. 1978-1981 ◽  
Author(s):  
R. Menozzi ◽  
L. Selmi ◽  
E. Sangiorgi ◽  
B. Ricco
Keyword(s):  
Latch Up
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