Analysis of Timing Error Due to Supply and Substrate Noise in an Inverter Based High-Speed Comparator

2019 ◽  
Author(s):  
Vijender Kumar Sharma ◽  
B. Dinesh Kumar ◽  
Muhammed Suhail Illikkal ◽  
Jai Narayan Tripathi ◽  
Navneet Gupta ◽  
...  
Keyword(s):  
High Speed ◽  
Substrate Noise ◽  
Timing Error

scholarly journals A novel timing-error based approach for high speed highly linear Mixing-DAC architectures

2014 ◽  
Author(s):  
Elbert Bechthum ◽  
Georgi Radulov ◽  
J. Briaire ◽  
Govert Geelen ◽  
Arthur van Roermund
Keyword(s):  
High Speed ◽  
Timing Error

scholarly journals The influence of software timing error on measurement accuracy of data acquisition

2019 ◽  
Vol 52 (7-8) ◽  
pp. 1008-1016
Author(s):  
Fan Wei ◽  
Jin Huaxue ◽  
Wang Yin ◽  
Fu Yuchen
Keyword(s):  
Data Acquisition ◽  
High Speed ◽  
Measurement Accuracy ◽  
Scientific Basis ◽  
Test System ◽  
Frequency Function ◽  
Time Data ◽  
Timing Error ◽  
Test Environment ◽  
Software Timing

The application of high-speed real-time data acquisition is becoming increasingly wide spread in industrial field, and its measurement accuracy is also increasing. The closed-loop test system of sine wave signal is constructed by the RIGOL’s DG1022 dual-channel signal source, DS1102C oscilloscope and PCI7489 multifunctional data acquisition card. Three kinds of timing methods, such as Visual Basics (VB) Timer control, multimedia timer function timing and query performance frequency function timing method, were carried out a series of comparative experiments. This paper analyzes the correlation characteristics of the measured voltage peak data, which includes mean value, variance, standard deviation, range, mutation system, deviation, kurtosis and so on, and then finds out the influence rules of software timing error on data acquisition and measurement accuracy. In the high-speed data acquisition, the repeatability error can be reduced from 84.22% to 0.62%, which provides scientific basis and reference for selecting software timing method in different test environment.

scholarly journals Design of the Optimum Execution Stage of Embedded Processors

1970 ◽  
Vol 8 (2) ◽  
pp. 104-112
Author(s):  
Masa-aki Fukase
Keyword(s):  
High Speed ◽  
Design Principle ◽  
Embedded Processors ◽  
Timing Error ◽  
Wave Pipelining ◽  
The One ◽  
Microprocessor Technology ◽  
And Control ◽  
Point Arithmetic ◽  
Speed Characteristic

We describe the optimum design of an execution stage for embedded processors. The execution stage is the core of embedded processors to treat basic applications for multimedia, communication and control. Considering algorithms in running such applications, the design principle of embedded processors is to achieve reliability, precision, low power, high speed and fast throughput altogether. However, it is hard to sufficiently clear the design principle by existing microprocessor technology. The one of difficult issues is the mixed sequence of integer and FP (floating point) arithmetic instructions. The different latencies of these instructions in a processor’s execution stage surely make the pipelined processing disturb and degrade throughput. The solution for this problem in this study is a wave-pipelined MFU (multifunctional unit) that is the multifunctionalization and wave-pipelining of different FUs (functional units). The high speed characteristic of wave-pipeling guarantees the reliability of processor behavior that is free from timing error. Thus, the waved MFU agrees well with overall trade-off design. In order to complement the shortage of the standard CAD tools, we explored the HS/SW (hardware/software) co-design for the waved MFU. Experimental results by using a 0.18-m CMOS standard cell technology showed the usefulness of this approach.

In-Situ Timing Error Predictor-Based Two-Cycle Adaptive Frequency Scaling System on an FPGA

2019 ◽  
Vol 29 (06) ◽  
pp. 2050098
Author(s):  
Minh Tung Dam ◽  
Van Toan Nguyen ◽  
Jeong-Gun Lee
Keyword(s):  
High Speed ◽  
Clock Cycle ◽  
Ring Oscillator ◽  
Target System ◽  
Clock Frequency ◽  
Frequency Scaling ◽  
Timing Error ◽  
Functional Correctness ◽  
Dynamic Frequency

In this paper, a timing error predictor (TEP) for adaptive frequency scaling (AFS) is proposed on a field-programmable gate array (FPGA). The use of TEP-based AFS can minimize large timing margin which is added to a clock cycle time for tolerating process, voltage, and temperature (PVT) variations. On an FPGA, in general, the typical dynamic frequency scaling has used the feature of dynamic frequency synthesis (DFS) in a digital clock manager (DCM). However, it has a long locking time. Moreover, during the DCM reconfiguration for generating a new frequency, the lock signal of the DCM can be lost and it leads to possible glitches or spikes at the output. In this work, a variable-length ring oscillator (VLRO), which employs a high-speed carry chain in an FPGA, is proposed to replace the DCM for changing the frequency within one clock cycle without introducing any glitches. Furthermore, an in-situ TEP, which detects timing errors, is combined with VLRO to further reduce the timing margin of a target system. Our proposed in-situ TEP-based AFS scheme is applied to a [Formula: see text]-bit multiplier and implemented on a Spartan-6 FPGA device (XFC6SLX45). The functional correctness of the TEP is verified under various DC supply voltages and operating frequencies. The experimental results show that the proposed TEP-based AFS system switches the clock frequency correctly within two clock cycles and improves circuit performance up to [Formula: see text] the nominal operating condition by minimizing the timing margin.

CMOS EIGHT-TRANSISTOR MEMORY CELL FOR LOW-DYNAMIC-POWER HIGH-SPEED EMBEDDED SRAM

2008 ◽  
Vol 17 (05) ◽  
pp. 845-863 ◽  
Author(s):  
SALEH M. ABDEL-HAFEEZ ◽  
ANAS S. MATALKAH
Keyword(s):  
High Speed ◽  
Average Power ◽  
Memory Cell ◽  
Timing Synchronization ◽  
Substrate Noise ◽  
Large Coupling ◽  
Average Power Consumption ◽  
Sram Design ◽  
Simulation Results ◽  
Embedded Sram

Embedded SRAM design with high noise margin between read and write, low power, low supply voltages, and high speed become essential features in VLSI embedded applications. The complete embedded SRAM design of self-timing synchronization is proposed based on the CMOS eight-transistor (8T-Cell) memory cell circuit. The cell is based on the traditional six-transistor (6T-Cell) cross-coupled invertors with the addition of two NMOS transistors for separate read buffer circuit. The read buffer structure is based on pre-charging the read bit-line during the low value of read clock and evaluating the read bit-line during the high value of read clock, thereby maintaining one active line per column and eliminating the use of traditional sense amplifier with all its synchronization schemes. The simulation results show that the embedded SRAM of size 128-bit × 128-bit is operating at a maximum frequency of 200 MHz for Write and Read clock cycles with 1.62 V power supply, and measures a total average power consumption of 22.60 mW. All simulation results were conducted on 0.18 μm TSMC single poly and three layers of metals measuring a cell area of 2.2 × 3.0 μ m 2. The circuit is not meant to replace the SRAM with 6T-Cell transistor structure; however, it is attractive for applications related to high density with automation road-map design, such as graphic and network processor chips. In these applications, memory sizes are introduced in many different irregular geometries and uses all over the chip with storage sizes less than 20 k-bit, in addition, it is susceptible to large substrate noise as well as large coupling wire routing.

Microfabrication research at the National Submicron Facility

1983 ◽  
Vol 41 ◽  
pp. 86-89
Author(s):  
E.D. Wolf
Keyword(s):  
Integrated Circuits ◽  
Particle Physics ◽  
High Speed ◽  
New Technology ◽  
High Energy ◽  
High Energy Particle ◽  
New Science ◽  
Wide Range ◽  
Intermediate Domain ◽  
Circuit Function

Most microelectronics devices and circuits operate faster, consume less power, execute more functions and cost less per circuit function when the feature-sizes internal to the devices and circuits are made smaller. This is part of the stimulus for the Very High-Speed Integrated Circuits (VHSIC) program. There is also a need for smaller, more sensitive sensors in a wide range of disciplines that includes electrochemistry, neurophysiology and ultra-high pressure solid state research. There is often fundamental new science (and sometimes new technology) to be revealed (and used) when a basic parameter such as size is extended to new dimensions, as is evident at the two extremes of smallness and largeness, high energy particle physics and cosmology, respectively. However, there is also a very important intermediate domain of size that spans from the diameter of a small cluster of atoms up to near one micrometer which may also have just as profound effects on society as “big” physics.

Vacuum System to Minimize the Specimen Contamination of High-Performance EM

1977 ◽  
Vol 35 ◽  
pp. 68-69
Author(s):  
N. Yoshimura ◽  
K. Shirota ◽  
T. Etoh
Keyword(s):  
Electron Microscope ◽  
High Speed ◽  
High Performance ◽  
High Vacuum ◽  
Vacuum System ◽  
Pump System ◽  
Pumping System ◽  
Diffusion Pump ◽  
Almost All ◽  
Cascade Type

One of the most important requirements for a high-performance EM, especially an analytical EM using a fine beam probe, is to prevent specimen contamination by providing a clean high vacuum in the vicinity of the specimen. However, in almost all commercial EMs, the pressure in the vicinity of the specimen under observation is usually more than ten times higher than the pressure measured at the punping line. The EM column inevitably requires the use of greased Viton O-rings for fine movement, and specimens and films need to be exchanged frequently and several attachments may also be exchanged. For these reasons, a high speed pumping system, as well as a clean vacuum system, is now required. A newly developed electron microscope, the JEM-100CX features clean high vacuum in the vicinity of the specimen, realized by the use of a CASCADE type diffusion pump system which has been essentially improved over its predeces- sorD employed on the JEM-100C.

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