In-Situ Timing Error Predictor-Based Two-Cycle Adaptive Frequency Scaling System on an FPGA

2019 ◽  
Vol 29 (06) ◽  
pp. 2050098
Author(s):  
Minh Tung Dam ◽  
Van Toan Nguyen ◽  
Jeong-Gun Lee
Keyword(s):  
High Speed ◽  
Clock Cycle ◽  
Ring Oscillator ◽  
Target System ◽  
Clock Frequency ◽  
Frequency Scaling ◽  
Timing Error ◽  
Functional Correctness ◽  
Dynamic Frequency

In this paper, a timing error predictor (TEP) for adaptive frequency scaling (AFS) is proposed on a field-programmable gate array (FPGA). The use of TEP-based AFS can minimize large timing margin which is added to a clock cycle time for tolerating process, voltage, and temperature (PVT) variations. On an FPGA, in general, the typical dynamic frequency scaling has used the feature of dynamic frequency synthesis (DFS) in a digital clock manager (DCM). However, it has a long locking time. Moreover, during the DCM reconfiguration for generating a new frequency, the lock signal of the DCM can be lost and it leads to possible glitches or spikes at the output. In this work, a variable-length ring oscillator (VLRO), which employs a high-speed carry chain in an FPGA, is proposed to replace the DCM for changing the frequency within one clock cycle without introducing any glitches. Furthermore, an in-situ TEP, which detects timing errors, is combined with VLRO to further reduce the timing margin of a target system. Our proposed in-situ TEP-based AFS scheme is applied to a [Formula: see text]-bit multiplier and implemented on a Spartan-6 FPGA device (XFC6SLX45). The functional correctness of the TEP is verified under various DC supply voltages and operating frequencies. The experimental results show that the proposed TEP-based AFS system switches the clock frequency correctly within two clock cycles and improves circuit performance up to [Formula: see text] the nominal operating condition by minimizing the timing margin.

scholarly journals Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs

2011 ◽  
Vol 2011 ◽  
pp. 1-12 ◽  
Author(s):  
Christian Schuck ◽  
Bastian Haetzer ◽  
Jürgen Becker
Keyword(s):  
Performance Management ◽  
High Speed ◽  
Clock Frequency ◽  
Frequency Scaling ◽  
Clock Networks ◽  
Digital Clock ◽  
Dynamic Frequency Scaling ◽  
Global Clock ◽  
Clock Distribution Network ◽  
Dynamic Frequency

Xilinx Virtex-II family FPGAs support an advanced low-skew clock distribution network with numerous global clock nets to support high-speed mixed frequency designs. Digital Clock Managers in combination with Global Clock Buffers are already in place to generate the desired frequency and to drive the clock networks with different sources, respectively. Currently, almost all designs run at a fixed clock frequency determined statically during design time. Such systems cannot take the full advantage of partial and dynamic self-reconfiguration. Therefore, we introduce a new methodology that allows the implemented hardware to dynamically self-adopt the clock frequency during runtime by reconfiguring the Digital Clock Managers. We also present a method for online speed monitoring which is based on a two-dimensional online routing. The created speed maps of the FPGA area can be used as an input for the dynamic frequency scaling. Figures for reconfiguration performance and power savings are given. Further, the tradeoffs for reconfiguration effort using this method are evaluated. Results show the high potential and importance of the distributed dynamic frequency scaling method with little additional overhead.

Effectiveness of DFS Tuning on Java Server Workload

2015 ◽  
Vol 25 (01) ◽  
pp. 1640005 ◽  
Author(s):  
Hitoshi Oi
Keyword(s):  
Power Consumption ◽  
Sampling Period ◽  
Threshold Level ◽  
Load Level ◽  
Clock Frequency ◽  
Frequency Scaling ◽  
Dynamic Frequency Scaling ◽  
Maximum Reduction ◽  
Dynamic Frequency

Dynamic frequency scaling (DFS) is a feature commonly found in modern processors. It lowers the clock frequency of a core according to the load level and reduces the power consumption. In this paper, we present a case study of tuning DFS parameters on a platform with an AMD Phenom II X6 using the SPECjEnterprise2010 (jEnt10) and SPECjbb2005 (jbb05) as the workload. In jEnt10, a longer sampling period of core utilization (up to 1.5[Formula: see text]s) reduced the power by 6[Formula: see text]Watt at 25% load level. At 50% load level, combining it with an increased threshold level (98%) to switch the clock frequency further reduced the power consumption by up to 10[Formula: see text]Watt. In jbb05, stretching the sampling period was only effective up to 0.5[Formula: see text]s. The maximum reduction was observed at around 60% load level. Raising the threshold level was not effective for jbb05.

A Carry Chain-Based ADMFC Design on an FPGA for EMI Reduction and Noise Compensation

2018 ◽  
Vol 28 (01) ◽  
pp. 1950018 ◽  
Author(s):  
Minh Tung Dam ◽  
Van Toan Nguyen ◽  
Jeong-Gun Lee
Keyword(s):  
Electromagnetic Interference ◽  
High Speed ◽  
Supply Voltage ◽  
Low Frequency ◽  
Working Environment ◽  
Sensor Nodes ◽  
Ring Oscillator ◽  
Clock Frequency ◽  
Voltage Variation ◽  
Field Programmable

An all-digital multi-frequency clocking (ADMFC) circuit is proposed to reduce electromagnetic interference (EMI) on a field-programmable gate array (FPGA) architecture, while supporting dynamic adaptation to voltage noises. The proposed ADMFC uses dedicated high-speed carry chain paths in an FPGA to finely adjust the clock frequency by controlling the number of carry propagations on the carry chain logics (CARRY4 cells) in the delay line of a ring oscillator. Moreover, supply voltage variation and noise caused by circuit switchings can be compensated by dynamically adjusting the length of ripple carry propagations on the cascaded CARRY4 cells in response to the detected voltage variation. Finally, a selectable modulation profile is devised to provide a much suitable profile between two different profiles at run-time for the given noise constraints and working environment of a chip. Measurement results show that at the frequency of 44.6[Formula: see text]MHz, the ADMFC can obtain 17[Formula: see text]dB and 19.4[Formula: see text]dB EMI attenuations with a 7.5% spreading ratio when using triangular and sawtooth profiles, respectively. The proposed ADMFC is suitable for applications such as biological sensor nodes or IoT related systems which typically operate at a low-frequency band.

A 0.0052 mm2 COMPACT DIGITAL PLL IN 65 nm CMOS

2012 ◽  
Vol 21 (08) ◽  
pp. 1240026 ◽  
Author(s):  
ZHIHONG LUO ◽  
YEUNG ON AU ◽  
BENJAMIN LAU ◽  
HENRY LAW
Keyword(s):  
Clock Cycle ◽  
Cell Number ◽  
Ring Oscillator ◽  
Total Power ◽  
Nand Gate ◽  
Clock Frequency ◽  
Clock Jitter ◽  
Delay Cell ◽  
Wide Range ◽  
Reference Clock

A novel structure of digital phase locked loop (PLL) is presented in this paper. It uses digitally controlled oscillator (DCO) to generate the clock. At the beginning of each reference clock cycle, the DCO is fully reset and restarts to oscillate to prevent the long term jitter accumulation and increase the loop stability. It uses three types of digital delay control methods, including delay cell number adjust, delay cell load adjust and in cycle load adjust to digitally control the DCO output clock frequency, in order to get wider frequency range and smaller jitter. This digital PLL uses NAND gate as the basic delay cell of ring oscillator, which can completely reset DCO in a very short time. It uses binary search to achieve fast lock and uses shift chain to get better input clock jitter tolerance. This digital PLL has been silicon validated in GLOBALFOUNDRIES 65 nm Generic process. Its chip area is only 0.0052 mm2. In typical condition, DCO's frequency has a wide range between 550 MHz and 2.45 GHz. Its total power is around 1.4 mW when DCO's frequency is 1.8 GHz. This PLL can be locked very fast in 25 divided reference clock cycles, and its output clock jitter is around 18 ps.

An atomic-resolution microscope study of Al contracts on GaAs

1986 ◽  
Vol 44 ◽  
pp. 726-727
Author(s):  
Z. Liliental-Weber ◽  
C. Nelson ◽  
R. Ludeke ◽  
R. Gronsky ◽  
J. Washburn
Keyword(s):  
High Speed ◽  
Schottky Contacts ◽  
Detailed Knowledge ◽  
The Past ◽  
Semiconductor Interfaces ◽  
Deposited Metal ◽  
Microwave Applications ◽  
Free Interfaces ◽  
Potential Use

The properties of metal/semiconductor interfaces have received considerable attention over the past few years, and the Al/GaAs system is of special interest because of its potential use in high-speed logic integrated optics, and microwave applications. For such materials a detailed knowledge of the geometric and electronic structure of the interface is fundamental to an understanding of the electrical properties of the contact. It is well known that the properties of Schottky contacts are established within a few atomic layers of the deposited metal. Therefore surface contamination can play a significant role. A method for fabricating contamination-free interfaces is absolutely necessary for reproducible properties, and molecularbeam epitaxy (MBE) offers such advantages for in-situ metal deposition under UHV conditions

Laser Silicon Interaction Study on Ring Oscillators to Establish Temperature Voltage Dependency Trends on 14 nm and Future FinFET Technologies

2017 ◽  
Author(s):  
Gaurav Mattey ◽  
Lava Ranganathan
Keyword(s):  
High Speed ◽  
Laser Frequency ◽  
Ring Oscillator ◽  
Switching Speed ◽  
Dual Nature ◽  
Voltage Imaging ◽  
Multiple Cores ◽  
Speed Performance ◽  
Self Test ◽  
Frequency Changes

Abstract Critical speed path analysis using Dynamic Laser Stimulation (DLS) technique has been an indispensable technology used in the Semiconductor IC industry for identifying process defects, design and layout issues that limit product speed performance. Primarily by injecting heat or injecting photocurrent in the active diffusion of the transistors, the laser either slows down or speeds up the switching speed of transistors, thereby affecting the overall speed performance of the chip and revealing the speed limiting/enhancing circuits. However, recently on Qualcomm Technologies’ 14nm FinFET technology SOC product, the 1340nm laser’s heating characteristic revealed a Vt (threshold voltage) improvement behavior at low operating voltages which helped identify process issues on multiple memory array blocks across multiple cores failing for MBIST (Memory Built-in Self-test). In this paper, we explore the innovative approach of using the laser to study Vt shifts in transistors due to process issues. We also study the laser silicon interactions through scanning the 1340nm thermal laser on silicon and observing frequency shifts in a high-speed Ring Oscillator (RO) on 16nm FinFET technology. This revealed the normal and reverse Temperature Dependency Gate voltages for 16nm FinFET, thereby illustrating the dual nature of stimulation (reducing mobility and improving Vt) from a thermal laser. Frequency mapping through Laser Voltage Imaging (LVI) was performed on the Ring Oscillator (RO) using the 1340nm thermal laser, while concurrently stimulating the transistors of the RO. Spatial distribution of stimulation was studied by observing the frequency changes on LVI.

scholarly journals Spatially Resolved Experimental Modal Analysis on High-Speed Composite Rotors Using a Non-Contact, Non-Rotating Sensor

Sensors ◽  
2021 ◽  
Vol 21 (14) ◽  
pp. 4705
Author(s):  
Julian Lich ◽  
Tino Wollmann ◽  
Angelos Filippatos ◽  
Maik Gude ◽  
Juergen Czarske ◽  
...  
Keyword(s):  
High Speed ◽  
Natural Frequencies ◽  
Mode Shapes ◽  
Fiber Reinforced ◽  
Structural Dynamic ◽  
Spatially Resolved ◽  
Glass Fiber Reinforced ◽  
Vibration Responses ◽  
And Performance

Due to their lightweight properties, fiber-reinforced composites are well suited for large and fast rotating structures, such as fan blades in turbomachines. To investigate rotor safety and performance, in situ measurements of the structural dynamic behaviour must be performed during rotating conditions. An approach to measuring spatially resolved vibration responses of a rotating structure with a non-contact, non-rotating sensor is investigated here. The resulting spectra can be assigned to specific locations on the structure and have similar properties to the spectra measured with co-rotating sensors, such as strain gauges. The sampling frequency is increased by performing consecutive measurements with a constant excitation function and varying time delays. The method allows for a paradigm shift to unambiguous identification of natural frequencies and mode shapes with arbitrary rotor shapes and excitation functions without the need for co-rotating sensors. Deflection measurements on a glass fiber-reinforced polymer disk were performed with a diffraction grating-based sensor system at 40 measurement points with an uncertainty below 15 μrad and a commercial triangulation sensor at 200 measurement points at surface speeds up to 300 m/s. A rotation-induced increase of two natural frequencies was measured, and their mode shapes were derived at the corresponding rotational speeds. A strain gauge was used for validation.

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