A high performance MOSFET on selective buried oxide with improved short channel effects

2009 ◽  
Author(s):  
S. Qureshi ◽  
S.A. Loan ◽  
S.S.K. Iyer
Keyword(s):  
High Performance ◽  
Short Channel Effects ◽  
Short Channel ◽  
Buried Oxide ◽  
Channel Effects

CMOS DEVICES ARCHITECTURES AND TECHNOLOGY INNOVATIONS FOR THE NANOELECTRONICS ERA

2006 ◽  
Vol 16 (01) ◽  
pp. 193-219 ◽  
Author(s):  
S. DELEONIBUS ◽  
B. de SALVO ◽  
T. ERNST ◽  
O. FAYNOT ◽  
T. POIROUX ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Gate Dielectric ◽  
Low Voltage ◽  
Short Channel Effects ◽  
Short Channel ◽  
Trade Offs ◽  
Future System ◽  
The Future ◽  
Channel Effects

Innovations in electronics history have been possible because of the strong association of devices and materials research. The demand for low voltage, low power and high performance are the great challenges for engineering of sub 50nm gate length CMOS devices. Functional CMOS devices in the range of 5 nm channel length have been demonstrated. The alternative architectures allowing to increase devices drivability and reduce power are reviewed through the issues to address in gate/channel and substrate, gate dielectric as well as source and drain engineering. HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. It will be very difficult to compete with CMOS logic because of the low series resistance required to obtain high performance. By introducing new materials ( Ge , diamond/graphite Carbon, HiK, …), Si based CMOS will be scaled beyond the ITRS as the future System-on-Chip Platform integrating new disruptive devices. The association of C-diamond with HiK as a combination for new functionalized Buried Insulators, for example, will bring new ways of improving short channel effects and suppress self-heating. That will allow new optimization of Ion-Ioff trade offs. The control of low power dissipation and short channel effects together with high performance will be the major challenges in the future.

An Area and Energy Efficient RAM Cell Design in Quantum Dot Cellular Automata

2019 ◽  
Vol 16 (10) ◽  
pp. 4179-4187
Author(s):  
Amanpreet Sandhu ◽  
Sheifali Gupta
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Short Channel Effects ◽  
Short Channel ◽  
Quantum Dot Cellular Automata ◽  
Channel Effects

The Conventional Complementary Metal oxide semiconductor (CMOS) technology has been revolutionized from the past few decades. However, the CMOS circuit faces serious constraints like short channel effects, quantum effects, doping fluctuations at the nanoscale which limits them to further scaling down at nano meter range. Among various existing nanotechnologies, Quantum dot Cellular Automata (QCA) provides new solution at nanocircuit design. The technical advancement of the paper lies in designing a high performance RAM cell with less QCA cells, less occupational area and lower power dissipation characteristics. The design occupies 12.5% lower area, 16.6% lower input to output delay, and dissipates 18.26% lesser energy than the designs in the literature. The proposed RAMcell is robust due to lesser noise variations. Also it has less fabrication cost due to absence of rotated cells.

scholarly journals Bulk Junctionless Transistor (JLT) with Non-Uniform Doping: A high Performance and Scalable device

2019 ◽  
Vol 8 (6) ◽  
pp. 450-455
Keyword(s):  
High Performance ◽  
Electrical Performance ◽  
Short Channel Effects ◽  
Short Channel ◽  
Junctionless Transistor ◽  
Channel Effects ◽  
Distribution Parameters ◽  
20 Nm ◽  
Substrate Doping ◽  
Uniform Doping

In this paper we have presented the non-uniformly doped bulk Junctionless transistor (JLT) and investigated bulk-JLT and SOI-JLT with non-uniform doping in terms of its electrical performance parameters and short channel effects (SCEs) parameters comparatively. Effective thickness of channel depends on non-uniform doping distribution parameters and this affects the performance of bulk-JLT notably, however it is not so in case of SOI-JLT. The effect of non-uniform doping on electrical characteristics of JLTs (bulk and SOI) in terms of Subthreshold Slope (SS), ON-current, OFF-Current and ON/OFF current ratio has been investigated, and the non-uniformly doped bulk-JLT exhibits high ON/OFF ratio (109 for 20 nm Gate Length). Moreover, the non-uniformly doped bulk-JLT also shows improved short-channel effects (SCEs) parameters (such as Drain Induced Barrier Lowering, Threshold Voltage variations etc.) compared to SOI-JLT. Lastly, the effect of standard deviation, dielectric constant, substrate doping, and well biasing on the device performance are examined to further improve the performance of bulk-JLT independently.

scholarly journals Π-Shape Silicon Window for Controlling OFF-Current in Junctionless SOI MOSFET

2021 ◽  
Author(s):  
Mahsa Mehrad ◽  
Meysam Zareiee
Keyword(s):  
The Body ◽  
Maximum Temperature ◽  
The Novel ◽  
Short Channel Effects ◽  
Short Channel ◽  
Soi Mosfet ◽  
Buried Oxide ◽  
Novel Structure ◽  
Channel Effects ◽  
Channel Region

Abstract in this paper a modified junctionless transistor is proposed. The aim of the novel structure is controlling off-current using π-shape silicon window in the buried oxide under the source and the channel regions. The π-shape window changes the potential profile in the channel region in which the conduction band energy get away from the body Fermi energy and rebuild an electrostatic potential. Beside the significant reduced off-current, on current has acceptable value in the novel Silicon Region Junctionless MOSFET (SR-JMOSFET) than Conventional Junctionless MOSFET (C-JMOSFET). Moreover, replacing silicon material instead of silicon dioxide in the buried oxide causes reduced maximum temperature in the channel region. In this situation the heat could transfer to the π-shape silicon window and the temperature reduces in the active region, significantly.The simulation with the two-dimensional ATLAS simulator shows that short channel effects such as subthreshold and DIBL are controlled effectively in the SR-JMOSFET. Also, the optimum values of length and thickness of the π-shape window are defined to obtain the best behavior of the device.

Ultra-Thin Body and Buried Oxide (UTBB) SOI MOSFETs on Suppression of Short-Channel Effects (SCEs): A Review

2015 ◽  
Vol 1109 ◽  
pp. 257-261 ◽  
Author(s):  
Noraini Othman ◽  
Mohd Khairuddin Md Arshad ◽  
Syarifah Norfaezah Sabki ◽  
U. Hashim
Keyword(s):  
Oxide Thickness ◽  
Thin Body ◽  
Short Channel Effects ◽  
Short Channel ◽  
Soi Mosfet ◽  
Buried Oxide ◽  
Device Structures ◽  
Junctionless Transistor ◽  
Channel Effects ◽  
Silicon Thickness

This paper reviews the different UTBB SOI MOSFET structures and their superiority in suppressing short-channel effects (SCEs). As the gate length (Lg), buried oxide thickness (TBOX) and silicon thickness (Tsi) are scaled down, the severity of SCEs becomes significant. The different UTBB SOI MOSFET device structures introduced to suppress these SCEs are discussed. The effectiveness of these structures in managing the associated SCEs such as drain-induced barrier lowering (DIBL), subthreshold swing (SS) and off-state leakage current (Ioff) is also presented. Further evaluations are made on other competing CMOS technologies such as multigate MOSFETs (FinFETs, three-gates, four-gates) and junctionless transistor in controlling the SCEs.

Monte Carlo study of 50 nm-long single and dual-gate MODFETs: suppression of short-channel effects

1993 ◽  
Vol 3 (9) ◽  
pp. 1719-1728
Author(s):  
P. Dollfus ◽  
P. Hesto ◽  
S. Galdin ◽  
C. Brisset
Keyword(s):  
Monte Carlo ◽  
Monte Carlo Study ◽  
Short Channel Effects ◽  
Short Channel ◽  
Channel Effects ◽  
Dual Gate
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