An Improved iMemComp OR Gate and its Applications in Logic Circuits

Long Channel Keeper Based Open Loop Difference Amplifier Domino For Noise Tolerant Low Power Or Gates

International Journal of Innovative Technology and Exploring Engineering - Special Issue ◽

10.35940/ijitee.j1221.0881019 ◽

2019 ◽

Vol 8 (10) ◽

pp. 3331-3340

Keyword(s):

Power Consumption ◽

Noise Immunity ◽

Cmos Technology ◽

Logic Circuits ◽

Open Loop ◽

High Input ◽

Noise Tolerant ◽

Capacitive Loading ◽

Long Channel ◽

Or Gate

This paper proposes an open loop difference amplifier with long channel keeper technique for domino logic circuits implemented as wide fan in OR gate. Currently OR gates suffer from high capacitive loading and delays due to such loading. The proposed design uses single stage of comparison and dual keeper arrangement to generate and hold the output logic state. This technique effectively reduces the high input loading from capacitance and manages the power consumption by switching based on the generated difference voltage. As compared to standard footerless domino SFLD, the proposed design OLDA has shown to reduce power consumption by 42% in 64 bit configuration. It has increased average noise immunity by 2.03 times, while maintaining same speed as compared to SFLD. All simulations are done in CMOS technology with 90nm PTM LP models

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General Modeling Method of Threshold-Type Multivalued Memristor and Its Application in Digital Logic Circuits

International Journal of Bifurcation and Chaos ◽

10.1142/s0218127421502485 ◽

2021 ◽

Vol 31 (16) ◽

Author(s):

Xiaoyuan Wang ◽

Pu Li ◽

Chenxi Jin ◽

Zhekang Dong ◽

Herbert H. C. Iu

Keyword(s):

Logic Circuits ◽

Modeling Method ◽

Digital Logic ◽

Behavior Model ◽

Spice Model ◽

Behavior Models ◽

Or Gate

This paper presents a general modeling method for threshold-type multivalued memristors. Through this memristor modeling method, it is very simple to establish threshold-type memristor behavior models with different numbers of memristance elements, and these models are verified by numerical MATLAB simulations. A corresponding circuit-level SPICE model of the ternary memristor behavior model is developed and simulated in LTspice, shown to be consistent with the MATLAB results. Finally, the SPICE model is used to design the AND gate, OR gate, and three NOT gates of ternary state-based logic, and the effectiveness of the circuit is proved by LTSpice simulation.

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Reconfigurable CPLAG and Modified PFAL Adiabatic Logic Circuits

Advances in Electronics ◽

10.1155/2015/202131 ◽

2015 ◽

Vol 2015 ◽

pp. 1-10

Author(s):

Manoj Sharma ◽

Arti Noor

Keyword(s):

Circuit Design ◽

Power Dissipation ◽

Supply Voltage ◽

Average Power ◽

Size Variation ◽

Logic Circuits ◽

Adiabatic Logic ◽

Or Gate ◽

Universal Gate ◽

Circuit Family

Previously, authors have proposed CPLAG and MCPLAG circuits extracting benefits of CPL family implemented based upon semiadiabatic logic for low power VLSI circuit design along with gating concept. Also authors have communicated RCPLAG circuits adding another dimension of reconfigurability into CPLAG/MCPLAG circuits. Moving ahead, in this paper, authors have implemented/reconfigured RCPLAG universal Nand/And gate and universal Nor/Or gate for extracting behavior of dynamic positive edge triggered DFF. Authors have also implemented Adder/Subtractor circuit using different techniques. Authors have also reported modification in PFAL semiadiabatic circuit family to further reduce the power dissipation. Functionality of these is verified and found to be satisfactory. Further these are examined rigorously with voltage, Cload, temperature, and transistor size variation. Performance of these is examined with these variations with power dissipation, delays, rise, and fall times associated. From the analysis it is found that best operating condition for DFF based upon RCPLAG universal gate can be achieved at supply voltage lower than 3 V which can be used for different transistor size up to 36 μm. Average power dissipation is 0.2 μW at 1 V and 30 μW at 2 V at 100 ff Cload 25°C approximately. Average power dissipated by CPLAG Adder/Subtractot is 58 μW. Modified PFAL circuit reduces average power by 9% approximately.

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Piezophototronic gated optofluidic logic computations empowering intrinsic reconfigurable switches

Nature Communications ◽

10.1038/s41467-019-12148-y ◽

2019 ◽

Vol 10 (1) ◽

Cited By ~ 4

Author(s):

Yuvasree Purusothaman ◽

Nagamalleswara Rao Alluri ◽

Arunkumar Chandrasekhar ◽

Vivekananthan Venkateswaran ◽

Sang-Jae Kim

Keyword(s):

Compressive Strain ◽

Logic Circuits ◽

Boolean Circuits ◽

Logic Device ◽

Metal Semiconductor Metal ◽

Metal Interfaces ◽

On Chip ◽

Logic Operations ◽

Scale Integration ◽

Or Gate

Abstract Optofluidic nano/microsystems have advanced the realization of Boolean circuits, with drastic progression to achieve extensive scale integration of desirable optoelectronics to investigate multiple logic switches. In this context, we demonstrate the optofluidic logic operations with interfacial piezophototronic effect to promote multiple operations of electronic analogues. We report an optofluidic Y-channeled logic device with tunable metal-semiconductor-metal interfaces through mechanically induced strain elements. We investigate the configuration of an OR gate in a semiconductor-piezoelectric zinc oxide nanorod-manipulated optofluidic sensor, and its direct reconfiguration to logic AND through compressive strain-induced (−1%) piezoelectric negative polarizations. The exhibited strategy in optofluidic systems implemented with piezophototronic concept enables direct-on chip working of OR and AND logic with switchable photocurrent under identical analyte. Featured smart intrinsic switching between the Boolean optoelectronic gates (OR↔AND) ultimately reduces the need for cascaded logic circuits to operate multiple logic switches on-a-chip.

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Precise Control of Gold Nanoparticles on DNA Origami for Logic Operation

Journal of Nanomaterials ◽

10.1155/2019/4890326 ◽

2019 ◽

Vol 2019 ◽

pp. 1-9 ◽

Cited By ~ 1

Author(s):

Kuiting Chen ◽

Xiang Li ◽

Jing Yang

Keyword(s):

Gold Nanoparticles ◽

Self Assembly ◽

Structural Control ◽

Large Scale ◽

Logic Gate ◽

Logic Circuits ◽

Dna Origami ◽

Precise Control ◽

Logic Operation ◽

Or Gate

Owing to their capacity for accurate structural control and complex programmability, DNA molecules have been extensively studied in relation to the construction of nanodevices. However, the existing logic gate sections based on DNA self-assembly were independent of each other, which hampered the development of large-scale integrated DNA circuits. Herein, we have explored a logic operation device with excellent scalability based on assembling and selectively releasing AuNPs on DNA origami, and have performed YES gate, OR gate, AND gate, and three-input composite gate. In the experiment, the logic operation result is detected by gel analysis and TEM image. The resolution of the output signals was greatly improved by determining the releasing of AuNPs from two-layer honeycomb origami. Our study provides a promising approach for building more complex large-scale DNA logic circuits.

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Logic Gates Formed by Perturbations in an Asynchronous Game of Life

Symmetry ◽

10.3390/sym13050907 ◽

2021 ◽

Vol 13 (5) ◽

pp. 907

Author(s):

Yoshihiko Ohzawa ◽

Yukio-Pegio Gunji

Keyword(s):

Logic Gate ◽

Logic Gates ◽

Logic Circuits ◽

The Other ◽

Probabilistic Logic ◽

Two Dimensional ◽

Game Of Life ◽

The Subject ◽

Logical Gate ◽

Or Gate

The game of life (GL), a type of two-dimensional cellular automaton, has been the subject of many studies because of its simple mechanism and complex behavior. In particular, the construction of logic circuits using the GL has helped to extend the concept of computation. Conventional logic circuits assume deterministic transitions due to the synchronicity of the classic GL. However, they are fragile to noise and cannot maintain the expected behavior in an environment with noise. In this study, a probabilistic logic gate model was constructed using perturbations in an asynchronous game of life (AGL). Since our asynchronous automaton had no heterogeneity in either the horizontal or vertical directions, it was symmetrical with respect to spatial structure. On the other hand, the construction of the logical gate was implemented to contain heterogeneity in the horizontal or vertical directions, which could allow an AND gate and an OR gate in a single system. It was based on the phase transition between connected and unconnected phases, which is newly discovered in this study. In the model, perturbations symmetrically entail operations successful and unsuccessful, and this symmetrical double action is given not to interfere with established operations but to make operations possible. Therefore, this model had a different meaning from logic gates that exclude perturbations or use them externally. The idea of this perturbation is analogous to the inherent noise that destroys and generates structures in biological swarms.

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