A novel high-speed 4-bit carry generator with a new structure for arithmetic operations

2014 ◽  
Author(s):  
Mehdi Ghasemzadeh ◽  
Neda Mohabbatian ◽  
Amin Akbari ◽  
Khayrollah Hadidi ◽  
Abdullah Khoei
Keyword(s):  
High Speed ◽  
Arithmetic Operations

Application of Arithmetic Operations Method in Single Pair-Pole Magnetic Encoder

2011 ◽  
Vol 128-129 ◽  
pp. 85-91
Author(s):  
Yi Fan Zeng ◽  
Rui Li
Keyword(s):  
High Speed ◽  
Angle Measurement ◽  
Single Pair ◽  
Nonlinear Correction ◽  
Arithmetic Operations ◽  
Rotational Angle ◽  
Voltage Signal ◽  
Fpga Chip ◽  
Novel Method ◽  
Hall Sensors

This paper proposes a novel method called arithmetic operations to analyze and process the generated voltage-signal from the single pair-pole magnetic encoder. Dual orthogonal voltage-signals are generated by two vertical hall sensors which are placed in the bottom of a columned magnet. When signals pass A/D converter, the quadrant determination, arithmetic operations and nonlinear correction in FPGA chip are performed before the values of rotational angle are displayed on the LED. This paper also designs and implements the single pair-pole magnetic encoder which has advantages such as high-speed, high-resolution and high-accuracy in the area of angle measurement.

A Novel and Very Fast 4-2 Compressor for High Speed Arithmetic Operations

2012 ◽  
Vol E95-C (4) ◽  
pp. 710-712 ◽  
Author(s):  
Amir FATHI ◽  
Sarkis AZIZIAN ◽  
Khayrollah HADIDI ◽  
Abdollah KHOEI
Keyword(s):  
High Speed ◽  
Arithmetic Operations

scholarly journals RECONFIGURABLE COMPUTING MODULAR SYSTEM

2021 ◽  
Vol 1 (1) ◽  
pp. 194-207
Author(s):  
S. S. Shevelev
Keyword(s):  
Information Processing ◽  
Reconfigurable Computing ◽  
High Speed ◽  
Computing System ◽  
Parallel Structure ◽  
Modular System ◽  
Switching Systems ◽  
Arithmetic Operations ◽  
Computing Systems ◽  
Logical Operations

Context. Modern general purpose computers are capable of implementing any algorithm, but when solving certain problems in terms of processing speed they cannot compete with specialized computing modules. Specialized devices have high performance, effectively solve the problems of processing arrays, artificial intelligence tasks, and are used as control devices. The use of specialized microprocessor modules that implement the processing of character strings, logical and numerical values, represented as integers and real numbers, makes it possible to increase the speed of performing arithmetic operations by using parallelism in data processing. Objective. To develop principles for constructing microprocessor modules for a modular computing system with a reconfigurable structure, an arithmetic-symbolic processor, specialized computing devices, switching systems capable of configuring microprocessors and specialized computing modules into a multi-pipeline structure to increase the speed of performing arithmetic and logical operations, high-speed design algorithms specialized processors-accelerators of symbol processing. To develop algorithms, structural and functional diagrams of specialized mathematical modules that perform arithmetic operations in direct codes on neural-like elements and systems for decentralized control of the operation of blocks. Method. An information graph of the computational process of a modular system with a reconstructed structure has been built. Structural and functional diagrams, algorithms that implement the construction of specialized modules for performing arithmetic and logical operations, search operations and functions for replacing occurrences in processed words have been developed. Software has been developed for simulating the operation of an arithmetic-symbolic processor, specialized computing modules, and switching systems. Results. A block diagram of a reconfigurable computing modular system has been developed, which consists of compatible functional modules, it is capable of static and dynamic reconfiguration, has a parallel structure for connecting the processor and computing modules through the use of interface channels. The system consists of an arithmetic-symbolic processor, specialized computing modules and switching systems, performs specific tasks of symbolic information processing, arithmetic and logical operations. Conclusions. The architecture of reconfigurable computing systems can change dynamically during their operation. It becomes possible to adapt the architecture of a computing system to the structure of the problem being solved, to create problem-oriented computers, the structure of which corresponds to the structure of the problem being solved. As the main computing element in reconfigurable computing systems, not universal microprocessors are used, but programmable logic integrated circuits, which are combined using high-speed interfaces into a single computing field. Reconfigurable multipipeline computing systems based on fields are an effective tool for solving streaming information processing and control problems.

Device for Calculating Logical and Arithmetic Operations

2021 ◽  
Vol 12 (7) ◽  
pp. 350-357
Author(s):  
S. S. Shevelev ◽  
Keyword(s):  
Fixed Point ◽  
High Speed ◽  
High Performance ◽  
Arithmetic Operations ◽  
Structural Scheme ◽  
Computing Systems ◽  
Logical Operations ◽  
Addition And Subtraction

A device has been developed that performs logical and arithmetic operations, which can be used to create high-performance, high-speed computing systems. Specialized blocks perform logical operations: AND, OR, NOT, arith­metic operations: addition and subtraction of binary numbers. Arithmetic operations are performed in direct fixed-point codes. The device is presented in the form of a structural scheme, structural and functional schemes of blocks and an algorithm for the operation of the device.

scholarly journals Design of high speed Wallace tree multiplier using 8-2 and 4-2 adder compressors

2018 ◽  
Vol 7 (4) ◽  
pp. 2386
Author(s):  
E Jagadeeswara Rao ◽  
K Jayaram Kumar ◽  
Dr. T. V. Prasad
Keyword(s):  
High Speed ◽  
Propagation Delay ◽  
Digital Systems ◽  
Fir Filters ◽  
Partial Product ◽  
Arithmetic Operations ◽  
Reduction Stage ◽  
Wallace Tree ◽  
Dsp Processors ◽  
Wallace Tree Multiplier

Multiplication is one of the most common arithmetic operations employed in digital systems such as FIR filters and DSP processors but multipliers are the most time, area, and power consuming circuits. Improvement in any of these parameters can be advantageous for improv-ing the efficiency of the circuit. High-speed multiplier which uses the high-speed adder is designed based on the Wallace tree concept in this paper. In this paper first we present an approach towards the reduction of delay in Wallace tree multipliers by using 8:2 and 4:2 adder com-pressors, in the partial product reduction stage. The proposed design is also compared to the Wallace Tree multiplier which uses 4:2 and 8:2 adder compressors in terms of propagation delay. The proposed design enhances speed of the system by 74.1% compared to the conven-tional Wallace Tree multiplier, while 24.1 % reduction was achieved in the delay of the system relative to Wallace tree multiplier with 16-bit adder with one of the 8-2 adder compressors.  

FAST RESIDUE-TO-BINARY CONVERSION USING BASE EXTENSION AND THE CHINESE REMAINDER THEOREM

2007 ◽  
Vol 16 (03) ◽  
pp. 379-388 ◽  
Author(s):  
AMOS R. OMONDI
Keyword(s):  
Low Power ◽  
High Speed ◽  
Chinese Remainder Theorem ◽  
Arithmetic Operations ◽  
Reverse Conversion ◽  
Number Systems ◽  
Residue Number Systems ◽  
Base Extension ◽  
Residue Number ◽  
Conventional Notation

Residue number systems are attractive due to their basic arithmetic operations, such as addition and multiplication, are carry-free; this facilitates low-power, high-speed implementations. But converting from residue to conventional notation is generally problematic. In this paper, we propose a high-speed architecture for reverse conversion; this is based on Base Extension and the Chinese Remainder Theorem.

scholarly journals Implementation of High Speed Vedic Multiplier Using Vertical and Crosswise Algorithm

2018 ◽  
Vol 6 (1) ◽  
pp. 36
Author(s):  
G. Vadiraj ◽  
K. Shivanand ◽  
B. Sampat ◽  
G. Subramanya Nayak
Keyword(s):  
High Speed ◽  
Digital Signal ◽  
Inner Product ◽  
Time Signal ◽  
Arithmetic Operations ◽  
Fundamental Function ◽  
Power Requirement ◽  
Vedic Multiplier ◽  
The Comparative Study ◽  
Dsp Applications

Multiplication is an important fundamental function in arithmetic operations. Multiplication-based operations such as Multiply and Accumulate (MAC) and inner product are some of the frequently used operations in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform(FFT), filtering and in microprocessors in its arithmetic and logic unit. Since multiplication dominates the execution time of most DSP algorithms, so there is a need of high speed multiplier. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications. In this project, the comparative study of Vedic multiplier and Sequential multiplier is done for low power requirement and high speed. The proposed architecture is based on the Vertical and Crosswise algorithm of ancient Indian Vedic Mathematics, which increases the speed of multiplier by reducing the number of clock cycles thus achieving the greater speed of the processor or system.

Microfabrication research at the National Submicron Facility

1983 ◽  
Vol 41 ◽  
pp. 86-89
Author(s):  
E.D. Wolf
Keyword(s):  
Integrated Circuits ◽  
Particle Physics ◽  
High Speed ◽  
New Technology ◽  
High Energy ◽  
High Energy Particle ◽  
New Science ◽  
Wide Range ◽  
Intermediate Domain ◽  
Circuit Function

Most microelectronics devices and circuits operate faster, consume less power, execute more functions and cost less per circuit function when the feature-sizes internal to the devices and circuits are made smaller. This is part of the stimulus for the Very High-Speed Integrated Circuits (VHSIC) program. There is also a need for smaller, more sensitive sensors in a wide range of disciplines that includes electrochemistry, neurophysiology and ultra-high pressure solid state research. There is often fundamental new science (and sometimes new technology) to be revealed (and used) when a basic parameter such as size is extended to new dimensions, as is evident at the two extremes of smallness and largeness, high energy particle physics and cosmology, respectively. However, there is also a very important intermediate domain of size that spans from the diameter of a small cluster of atoms up to near one micrometer which may also have just as profound effects on society as “big” physics.

Vacuum System to Minimize the Specimen Contamination of High-Performance EM

1977 ◽  
Vol 35 ◽  
pp. 68-69
Author(s):  
N. Yoshimura ◽  
K. Shirota ◽  
T. Etoh
Keyword(s):  
Electron Microscope ◽  
High Speed ◽  
High Performance ◽  
High Vacuum ◽  
Vacuum System ◽  
Pump System ◽  
Pumping System ◽  
Diffusion Pump ◽  
Almost All ◽  
Cascade Type

One of the most important requirements for a high-performance EM, especially an analytical EM using a fine beam probe, is to prevent specimen contamination by providing a clean high vacuum in the vicinity of the specimen. However, in almost all commercial EMs, the pressure in the vicinity of the specimen under observation is usually more than ten times higher than the pressure measured at the punping line. The EM column inevitably requires the use of greased Viton O-rings for fine movement, and specimens and films need to be exchanged frequently and several attachments may also be exchanged. For these reasons, a high speed pumping system, as well as a clean vacuum system, is now required. A newly developed electron microscope, the JEM-100CX features clean high vacuum in the vicinity of the specimen, realized by the use of a CASCADE type diffusion pump system which has been essentially improved over its predeces- sorD employed on the JEM-100C.

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