A negative conductance voltage gain enhancement technique for low voltage high speed CMOS op amp design

Author(s):  
Jie Yan ◽  
R.L. Geiger
2020 ◽  
Vol 29 (14) ◽  
pp. 2050220
Author(s):  
Rajasekhar Nagulapalli ◽  
Khaled Hayatleh ◽  
Steve Barker

A power-efficient, voltage gain enhancement technique for op-amps has been described. The proposed technique is robust against Process, Voltage and Temperature (PVT) variations. It exploits a positive feedback-based gain enhancement technique without any latch-up issue, as opposed to the previously proposed conductance cancellation techniques. In the proposed technique, four additional transconductance-stages (gm stages) are used to boost the gain of the main gm stage. The additional gm stages do not significantly increase the power dissipation. A prototype was designed in 65[Formula: see text]nm CMOS technology. It results in 81[Formula: see text]dB voltage gain, which is 21[Formula: see text]dB higher than the existing gain-boosting technique. The proposed op-amp works with as low a power supply as 0.8[Formula: see text]V, without compromising the performance, whereas the traditional gain-enhancement techniques start losing gain below a 1.1[Formula: see text]V supply. The circuit draws a total static current of 295[Formula: see text][Formula: see text]A and occupies 5000[Formula: see text][Formula: see text]m2 of silicon area.


Author(s):  
Furkan Barin ◽  
Ertan Zencir

In this paper, an ultra-wideband fully differential two-stage telescopic 65-nm CMOS op-amp is presented, which uses low-voltage design techniques such as level shifter circuits and low-voltage cascode current mirrors. The designed op-amp consists of two stages. While the telescopic first stage provides high speed and low swing, the second stage provides high gain and large swing. Common-mode feedback circuits (CMFB), which contain five transistors OTA and sensing resistors, are used to set the first-stage output to a known value. The designed two-stage telescopic operational amplifier has 41.04[Formula: see text]dB lower frequency gain, 1.81[Formula: see text]GHz gain-bandwidth product (GBW) and 51.9∘ phase margin under 5[Formula: see text]pF load capacitance. The design consumes a total current of 11.9[Formula: see text]mA from a 1.2-V supply voltage. Presented fully differential two-stage telescopic op-amp by using low-voltage design techniques is suitable for active filter in vehicle-to-everything (V2X) applications with 120[Formula: see text][Formula: see text]m[Formula: see text]m layout area.


Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1410
Author(s):  
Luis Henrique Rodovalho ◽  
Orazio Aiello ◽  
Cesar Ramos Rodrigues

This paper proposes topological enhancements to increase voltage gain of ultra-low-voltage (ULV) inverter-based OTAs. The two proposed improvements rely on adoption of composite transistors and forward-body-biasing. The impact of the proposed techniques on performance figures is demonstrated through simulations of two OTAs. The first OTA achieves a 39 dB voltage gain, with a power consumption of 600 pW and an active area of 447 μm2. The latter allies the forward-body-bias approach with the benefit of the independently biased composite transistors. By combining both solutions, voltage gain is raised to 51 dB, consuming less power (500 pW) at the cost of an increased area of 727 μm2. The validation has been performed through post-layout simulations with the Cadence Analog Design Environment and the TSMC 180 nm design kit, with the supply voltage ranging from 0.3 V to 0.6 V.


Nanophotonics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 1765-1773
Author(s):  
Yi Zhang ◽  
Jianfeng Gao ◽  
Senbiao Qin ◽  
Ming Cheng ◽  
Kang Wang ◽  
...  

Abstract We design and demonstrate an asymmetric Ge/SiGe coupled quantum well (CQW) waveguide modulator for both intensity and phase modulation with a low bias voltage in silicon photonic integration. The asymmetric CQWs consisting of two quantum wells with different widths are employed as the active region to enhance the electro-optical characteristics of the device by controlling the coupling of the wave functions. The fabricated device can realize 5 dB extinction ratio at 1446 nm and 1.4 × 10−3 electrorefractive index variation at 1530 nm with the associated modulation efficiency V π L π of 0.055 V cm under 1 V reverse bias. The 3 dB bandwidth for high frequency response is 27 GHz under 1 V bias and the energy consumption per bit is less than 100 fJ/bit. The proposed device offers a pathway towards a low voltage, low energy consumption, high speed and compact modulator for silicon photonic integrated devices, as well as opens possibilities for achieving advanced modulation format in a more compact and simple frame.


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