scholarly journals A Positive Feedback-Based Op-Amp Gain Enhancement Technique for High-Precision Applications

2020 ◽  
Vol 29 (14) ◽  
pp. 2050220
Author(s):  
Rajasekhar Nagulapalli ◽  
Khaled Hayatleh ◽  
Steve Barker
Keyword(s):  
Positive Feedback ◽  
Cmos Technology ◽  
Voltage Gain ◽  
Silicon Area ◽  
Power Efficient ◽  
Enhancement Technique ◽  
Op Amp ◽  
Gain Enhancement ◽  
Pvt Variations ◽  
Boosting Technique

A power-efficient, voltage gain enhancement technique for op-amps has been described. The proposed technique is robust against Process, Voltage and Temperature (PVT) variations. It exploits a positive feedback-based gain enhancement technique without any latch-up issue, as opposed to the previously proposed conductance cancellation techniques. In the proposed technique, four additional transconductance-stages (gm stages) are used to boost the gain of the main gm stage. The additional gm stages do not significantly increase the power dissipation. A prototype was designed in 65[Formula: see text]nm CMOS technology. It results in 81[Formula: see text]dB voltage gain, which is 21[Formula: see text]dB higher than the existing gain-boosting technique. The proposed op-amp works with as low a power supply as 0.8[Formula: see text]V, without compromising the performance, whereas the traditional gain-enhancement techniques start losing gain below a 1.1[Formula: see text]V supply. The circuit draws a total static current of 295[Formula: see text][Formula: see text]A and occupies 5000[Formula: see text][Formula: see text]m2 of silicon area.

scholarly journals Design of area-efficient GHz range current mode frequency synthesizer using standard CMOS technology

2019 ◽  
Vol 70 (4) ◽  
pp. 323-328
Author(s):  
Dan-Dan Zheng ◽  
Yu-Bin Li ◽  
Chang-Qi Wang ◽  
Kai Huang ◽  
Xiao-Peng Yu
Keyword(s):  
Frequency Synthesizer ◽  
Frequency Tuning ◽  
Supply Voltage ◽  
Current Mode ◽  
Cmos Technology ◽  
Mode Frequency ◽  
Loop Filter ◽  
Silicon Area ◽  
Power Efficient ◽  
A Current

Abstract In this paper, an area and power efficient current mode frequency synthesizer for system-on-chip (SoC) is proposed. A current-mode transformer loop filter suitable for low supply voltage is implemented to remove the need of a large capacitor in the loop filter, and a current controlled oscillator with additional voltage based frequency tuning mechanism is designed with an active inductor. The proposed design is further integrated with a fully programmable frequency divider to maintain a good balance among output frequency operating range, power consumption as well as silicon area. A test chip is implemented in a standard 0.13 µm CMOS technology, measurement result demonstrates that the proposed design has a working range from 916 MHz to 1.1 l GHz and occupies a silicon area of 0.25 mm2 while consuming 8.4 mW from a 1.2 V supply.

scholarly journals A Digital-to-Time Converter for Time-Mode Successive-Approximation Register Analog-to-Digital Converters

2021 ◽  
Author(s):  
Daniel Junehee Lee
Keyword(s):  
Power Consumption ◽  
Successive Approximation ◽  
Cmos Technology ◽  
Sar Adc ◽  
Least Significant Bit ◽  
Silicon Area ◽  
Analog To Digital ◽  
Power Efficient ◽  
Successive Approximation Register ◽  
Simulation Results

file:///C:/Users/MWF/Downloads/Lee, Daniel Junehee.The 8-bit digital-to-time converter (DTC) to be used for a time-mode successive-approximation register analog-to-digital converter (SAR ADC) with a minimum power consumption and silicon area is presented. The architecture and the drawbacks of a conventional voltage-mode SAR ADC are discussed. The principle of time-mode circuits and benefits of their applications to mixed-signal circuits are explained. The architecture of a time-mode SAR ADC is presented. The need for an area and power-efficient DTC to be used for a time-mode SAR ADC is discussed. The principle of a DTC is explained and prior works on a DTC are reviewed. The principle of a phase interpolator (PI), to be used for a DTC, is explained and prior works on digital PIs are reviewed. The design of the proposed DTC is presented. Each block of the proposed DTC is explained using schematic and layout views. Optimal slope of the input of the PI and the condition for linear phase interpolation are investigated. Simulation results of the proposed DTC designed in TSMC 65 nm 1.0 V CMOS technology are provided. According to simulation results with BSIM4.4 device models only, the time resolution of 0.33 ps, a maximum operation frequency of 2.53 G Hz, the power consumption of 1.38 mW, and peak differential nonlinearity (DNL) and integral nonlinearity (INL) less than 0.14 least significant bit (LSB) and 0.49 LSB, respectively, for a nominal process (TT) and a temperature condition (27 C°) are achieved.

scholarly journals Design and PVT Analysis of Robust, High Swing Folded Cascode Operational Amplifier

2019 ◽  
Vol 9 (2) ◽  
pp. 114-118
Keyword(s):  
Power Dissipation ◽  
Operational Amplifier ◽  
Low Voltage ◽  
Cmos Technology ◽  
Current Mirror ◽  
Op Amp ◽  
Multistage Amplifiers ◽  
Pvt Variations ◽  
Folded Cascode ◽  
Voltage Swing

The folded cascode operational amplifier (FCOA) designed in this paper is the single-pole operational amplifier (op amp). In this design, the conventional current mirror is replaced with wide swing current mirror to overcome the essential drawback of cascode configuration. In this paper, negative feedback is used to improve the small-signal gain and to ensure better stability than multistage amplifiers. This paper also aims at improving the output voltage swing, power dissipation and robustness of the op amp. The designed FCOA is proficient in achieving 67.44dB gain and 1.77V output swingat typical voltage for 180nm CMOS technology. The FCOA is highly stable with phase margin of 62.58º while dissipating 0.5mW power. This amplifier is further verified for variability analysis for Process, Voltage and Temperature (PVT) variations to check robustness. All together testing is done at 45 different PVT combinations and results are tabulated accordingly. At each corner temperature and voltage are varied for all together nine combinations to properly address the effect of PVT variations. The results shows that the op amp exhibits desired response at four corners (FF, TT, SS, and FS) of process, over -40º to 125º C temperature range. Also it is capable of operating at very low voltage up to 0.9V adequately showing reduction in power dissipation. Thus the designed op amp is low power, high swing and robust towards process, voltage and temperature variations.

scholarly journals A Digital-to-Time Converter for Time-Mode Successive-Approximation Register Analog-to-Digital Converters

2021 ◽  
Author(s):  
Daniel Junehee Lee
Keyword(s):  
Power Consumption ◽  
Successive Approximation ◽  
Cmos Technology ◽  
Sar Adc ◽  
Least Significant Bit ◽  
Silicon Area ◽  
Analog To Digital ◽  
Power Efficient ◽  
Successive Approximation Register ◽  
Simulation Results

file:///C:/Users/MWF/Downloads/Lee, Daniel Junehee.The 8-bit digital-to-time converter (DTC) to be used for a time-mode successive-approximation register analog-to-digital converter (SAR ADC) with a minimum power consumption and silicon area is presented. The architecture and the drawbacks of a conventional voltage-mode SAR ADC are discussed. The principle of time-mode circuits and benefits of their applications to mixed-signal circuits are explained. The architecture of a time-mode SAR ADC is presented. The need for an area and power-efficient DTC to be used for a time-mode SAR ADC is discussed. The principle of a DTC is explained and prior works on a DTC are reviewed. The principle of a phase interpolator (PI), to be used for a DTC, is explained and prior works on digital PIs are reviewed. The design of the proposed DTC is presented. Each block of the proposed DTC is explained using schematic and layout views. Optimal slope of the input of the PI and the condition for linear phase interpolation are investigated. Simulation results of the proposed DTC designed in TSMC 65 nm 1.0 V CMOS technology are provided. According to simulation results with BSIM4.4 device models only, the time resolution of 0.33 ps, a maximum operation frequency of 2.53 G Hz, the power consumption of 1.38 mW, and peak differential nonlinearity (DNL) and integral nonlinearity (INL) less than 0.14 least significant bit (LSB) and 0.49 LSB, respectively, for a nominal process (TT) and a temperature condition (27 C°) are achieved.

scholarly journals New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic

2011 ◽  
Vol 2011 ◽  
pp. 1-6 ◽  
Author(s):  
Kirti Gupta ◽  
Ranjana Sridhar ◽  
Jaya Chaudhary ◽  
Neeta Pandey ◽  
Maneesha Gupta
Keyword(s):  
Low Power ◽  
Positive Feedback ◽  
Cmos Technology ◽  
Performance Comparison ◽  
Power Efficient ◽  
Power Delay Product ◽  
Feedback Source ◽  
Design Techniques ◽  
A Performance

Two new design techniques to implement tristate circuits in positive feedback source-coupled logic (PFSCL) have been proposed. The first one is a switch-based technique while the second is based on the concept of sleep transistor. Different tristate circuits based on both techniques have been developed and simulated using 0.18 μm CMOS technology parameters. A performance comparison indicates that the tristate PFSCL circuits based on sleep transistor technique are more power efficient and achieve the lowest power delay product in comparison to CMOS-based and the switch-based PFSCL circuits.

scholarly journals Implementation of Power-Efficient Class AB Miller Amplifiers Using Resistive Local Common-Mode Feedback

2021 ◽  
Vol 11 (3) ◽  
pp. 31
Author(s):  
Anindita Paul ◽  
Mario Renteria-Pinon ◽  
Jaime Ramirez-Angulo ◽  
Ricardo Bolaños-Pérez ◽  
Héctor Vázquez-Leal ◽  
...  
Keyword(s):  
Current Efficiency ◽  
Figure Of Merit ◽  
Small Signal ◽  
Common Mode ◽  
Power Efficient ◽  
Class Ab ◽  
Op Amp ◽  
Class A ◽  
Wide Range ◽  
Quiescent Current

An approach to implement single-ended power-efficient static class-AB Miller op-amps with symmetrical and significantly enhanced slew-rate and accurately controlled output quiescent current is introduced. The proposed op-amp can drive a wide range of resistive and capacitive loads. The output positive and negative currents can be much higher than the total op-amp quiescent current. The enhanced performance is achieved by utilizing a simple low-power auxiliary amplifier with resistive local common-mode feedback that increases the quiescent power dissipation by less than 10%. The proposed class AB op-amp is characterized by significantly enhanced large-signal dynamic, static current efficiency, and small-signal figures of merits. The dynamic current efficiency is 15.6 higher, the static current efficiency is 8.9 times higher, and the small-signal figure of merit is 2.3 times higher than the conventional class-A op-amp. A global figure of merit that determines an op-amp’s ultimate speed is 6.33 times higher than the conventional class A op-amp.

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