Background:
The advancement of VLSI in the application of emerging nanotechnology
explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its
ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature
size. The QCA architectures are emerging as a potential alternative to the conventional complementary
metal oxide semiconductor (CMOS) technology.
Experimental:
Since the register unit has a crucial role in digital data transfer between the electronic
devices, such study leading to the design of cost-efficient and highly reliable QCA register
is expected to be a prudent area of research. A thorough survey on the existing literature shows
that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In-
Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design
parameters like effective area, delay, O-Cost, Costα, etc.
Results:
This work introduces a layered T gate for the design of the D flip flop (LTD unit), which
can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting
of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis
of LTD unit are also carried out in this work. The QCA design metrics for the general register
layouts using LTD unit is modeled.
Conclusion:
Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to
check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA
register layouts.
The Power Analysis of 1T-DRAM Cell with Different FET technologies
