A low-voltage swing latch for reduced power dissipation in high-frequency microprocessors

2005 ◽  
Author(s):  
Pong-Fei Lu ◽  
L. Sigal ◽  
N. Cao ◽  
P. Woltgens ◽  
R. Robertazzi ◽  
...  
Keyword(s):  
Power Dissipation ◽  
High Frequency ◽  
Low Voltage ◽  
Voltage Swing

scholarly journals Design and PVT Analysis of Robust, High Swing Folded Cascode Operational Amplifier

2019 ◽  
Vol 9 (2) ◽  
pp. 114-118
Keyword(s):  
Power Dissipation ◽  
Operational Amplifier ◽  
Low Voltage ◽  
Cmos Technology ◽  
Current Mirror ◽  
Op Amp ◽  
Multistage Amplifiers ◽  
Pvt Variations ◽  
Folded Cascode ◽  
Voltage Swing

The folded cascode operational amplifier (FCOA) designed in this paper is the single-pole operational amplifier (op amp). In this design, the conventional current mirror is replaced with wide swing current mirror to overcome the essential drawback of cascode configuration. In this paper, negative feedback is used to improve the small-signal gain and to ensure better stability than multistage amplifiers. This paper also aims at improving the output voltage swing, power dissipation and robustness of the op amp. The designed FCOA is proficient in achieving 67.44dB gain and 1.77V output swingat typical voltage for 180nm CMOS technology. The FCOA is highly stable with phase margin of 62.58º while dissipating 0.5mW power. This amplifier is further verified for variability analysis for Process, Voltage and Temperature (PVT) variations to check robustness. All together testing is done at 45 different PVT combinations and results are tabulated accordingly. At each corner temperature and voltage are varied for all together nine combinations to properly address the effect of PVT variations. The results shows that the op amp exhibits desired response at four corners (FF, TT, SS, and FS) of process, over -40º to 125º C temperature range. Also it is capable of operating at very low voltage up to 0.9V adequately showing reduction in power dissipation. Thus the designed op amp is low power, high swing and robust towards process, voltage and temperature variations.

scholarly journals Starter for Voltage Boost Converter to Harvest Thermoelectric Energy for Body-Worn Sensors

Energies ◽  
2021 ◽  
Vol 14 (14) ◽  
pp. 4092
Author(s):  
Grzegorz Blakiewicz ◽  
Jacek Jakusz ◽  
Waldemar Jendernalik
Keyword(s):  
Threshold Voltage ◽  
Low Voltage ◽  
Boost Converter ◽  
Mos Transistors ◽  
Weak Inversion ◽  
Thermoelectric Energy ◽  
On Chip ◽  
Voltage Swing ◽  
High Output Voltage ◽  
High Output

This paper examines the suitability of selected configurations of ultra-low voltage (ULV) oscillators as starters for a voltage boost converter to harvest energy from a thermoelectric generator (TEG). Important properties of particularly promising configurations, suitable for on-chip implementation are compared. On this basis, an improved oscillator with a low startup voltage and a high output voltage swing is proposed. The applicability of n-channel native MOS transistors with negative or near-zero threshold voltage in ULV oscillators is analyzed. The results demonstrate that a near-zero threshold voltage transistor operating in the weak inversion region is most advantageous for the considered application. The obtained results were used as a reference for design of a boost converter starter intended for integration in 180-nm CMOS X-FAB technology. In the selected technology, the most suitable transistor available with a negative threshold voltage was used. Despite using a transistor with a negative threshold voltage, a low startup voltage of 29 mV, a power consumption of 70 µW, and power conversion efficiency of about 1.5% were achieved. A great advantage of the proposed starter is that it eliminates a multistage charge pump necessary to obtain a voltage of sufficient value to supply the boost converter control circuit.

scholarly journals Distinct EEG seizure patterns reflect different seizure generation mechanisms

2015 ◽  
Vol 113 (7) ◽  
pp. 2840-2844 ◽  
Author(s):  
Pariya Salami ◽  
Maxime Lévesque ◽  
Jean Gotman ◽  
Massimo Avoli
Keyword(s):  
High Frequency ◽  
Channel Blocker ◽  
Seizure Activity ◽  
Low Voltage ◽  
High Frequency Oscillation ◽  
Seizure Onset ◽  
Frequency Oscillation ◽  
Oscillation Analysis ◽  
Pilocarpine Model ◽  
Generation Mechanisms

Low-voltage fast (LVF)- and hypersynchronous (HYP)-seizure onset patterns can be recognized in the EEG of epileptic animals and patients with temporal lobe epilepsy. Ripples (80–200 Hz) and fast ripples (250–500 Hz) have been linked to each pattern, with ripples predominating during LVF seizures and fast ripples predominating during HYP seizures in the rat pilocarpine model. This evidence led us to hypothesize that these two seizure-onset patterns reflect the contribution of neural networks with distinct transmitter signaling characteristics. Here, we tested this hypothesis by analyzing the seizure activity induced with the K+ channel blocker 4-aminopyridine (4AP, 4–5 mg/kg ip), which enhances both glutamatergic and GABAergic transmission, or the GABAA receptor antagonist picrotoxin (3–5 mg/kg ip); rats were implanted with electrodes in the hippocampus, the entorhinal cortex, and the subiculum. We found that LVF onset occurred in 82% of 4AP-induced seizures whereas seizures after picrotoxin were always HYP. In addition, high-frequency oscillation analysis revealed that 4AP-induced LVF seizures were associated with higher ripple rates compared with fast ripples ( P < 0.05), whereas picrotoxin-induced seizures contained higher rates of fast ripples compared with ripples ( P < 0.05). These results support the hypothesis that two distinct patterns of seizure onset result from different pathophysiological mechanisms.

Low-Voltage, High-Frequency Organic Transistors and Unipolar and Complementary Ring Oscillators on Paper

2018 ◽  
Vol 5 (2) ◽  
pp. 1800453 ◽  
Author(s):  
Ulrike Kraft ◽  
Tarek Zaki ◽  
Florian Letzkus ◽  
Joachim N. Burghartz ◽  
Edwin Weber ◽  
...  
Keyword(s):  
High Frequency ◽  
Low Voltage ◽  
Organic Transistors ◽  
Ring Oscillators

scholarly journals Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering

VLSI Design ◽  
2002 ◽  
Vol 15 (2) ◽  
pp. 547-553
Author(s):  
S. M. Rezaul Hasan ◽  
Yufridin Wahab
Keyword(s):  
Power Dissipation ◽  
Figure Of Merit ◽  
Low Voltage ◽  
Logic Gates ◽  
Base Layer ◽  
Cmos Process ◽  
Silicon Area ◽  
Dynamic Power ◽  
Analog Cmos ◽  
Power Delay Product

This paper explores the deterministic transistor reordering in low-voltage dynamic BiCMOS logic gates, for reducing the dynamic power dissipation. The constraints of load driving (discharging) capability and NPN turn-on delay for MOSFET reordered structures has been carefully considered. Simulations shows significant reduction in the dynamic power dissipation for the transistor reordered BiCMOS structures. The power-delay product figure-of-merit is found to be significantly enhanced without any associated silicon-area penalty. In order to experimentally verify the reduction in power dissipation, original and reordered structures were fabricated using the MOSIS 2 μm N-well analog CMOS process which has a P-base layer for bipolar NPN option. Measured results shows a 20% reduction in the power dissipation for the transistor reordered structure, which is in close agreement with the simulation.

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