scholarly journals Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering

VLSI Design ◽  
2002 ◽  
Vol 15 (2) ◽  
pp. 547-553
Author(s):  
S. M. Rezaul Hasan ◽  
Yufridin Wahab
Keyword(s):  
Power Dissipation ◽  
Figure Of Merit ◽  
Low Voltage ◽  
Logic Gates ◽  
Base Layer ◽  
Cmos Process ◽  
Silicon Area ◽  
Dynamic Power ◽  
Analog Cmos ◽  
Power Delay Product

This paper explores the deterministic transistor reordering in low-voltage dynamic BiCMOS logic gates, for reducing the dynamic power dissipation. The constraints of load driving (discharging) capability and NPN turn-on delay for MOSFET reordered structures has been carefully considered. Simulations shows significant reduction in the dynamic power dissipation for the transistor reordered BiCMOS structures. The power-delay product figure-of-merit is found to be significantly enhanced without any associated silicon-area penalty. In order to experimentally verify the reduction in power dissipation, original and reordered structures were fabricated using the MOSIS 2 μm N-well analog CMOS process which has a P-base layer for bipolar NPN option. Measured results shows a 20% reduction in the power dissipation for the transistor reordered structure, which is in close agreement with the simulation.

Low Power High Speed MISTY1 Cryptography Approaches

2018 ◽  
Vol 27 (13) ◽  
pp. 1850200 ◽  
Author(s):  
Abdoul Rjoub ◽  
Ehab M. Ghabashneh
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Logic Gate ◽  
Logic Gates ◽  
Portable Devices ◽  
Silicon Area ◽  
Dynamic Power ◽  
Conventional Design ◽  
Reduction Approach

The demand for high performance, low power/secured handheld equipment increased the need for high speed/low energy and efficient encryption/decryption algorithms. Recently, efficient techniques were suggested to increase the standard of security as well as the speed of portable and handheld devices. Also, those techniques cause increment in the lifetime of battery by reducing the total silicon capacitance and minimizing the switching activity. This paper presents two approaches to reduce the number of logic gates at S7 and S9 of MISTY1 in order to reduce the total delay time, power dissipation and silicon area. The Logic Gate Reduction Approach (LGRA) reduces the number of logic gates by applying Boolean Algebra rules and simplifications, while the Duplicated Gate Reduction Approach (DGRA) removes the redundant XOR and AND logic gates which form the S7 and S9 blocks ciphers. The LGRA approach shows that the throughput enhanced by 21.1% compared to the conventional design, the silicon area reduced by 26.8%, while the dynamic power dissipation is reduced by 21.7% on average. The DGRA approach shows that the throughput enhanced by 3.8% compared to the conventional design, the silicon area reduced by 31.7%, while the dynamic power dissipation is reduced by 27% on average. As a result, the proposed approaches could be fit for next generation of handheld and portable devices.

scholarly journals Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs

Electronics ◽  
2021 ◽  
Vol 10 (10) ◽  
pp. 1156
Author(s):  
Lorenzo Benvenuti ◽  
Alessandro Catania ◽  
Giuseppe Manfredini ◽  
Andrea Ria ◽  
Massimo Piotto ◽  
...  
Keyword(s):  
Low Voltage ◽  
Flicker Noise ◽  
Supply Voltage ◽  
Cmos Process ◽  
Clock Frequency ◽  
Design Environment ◽  
Ultra Low Power ◽  
Analog Cmos ◽  
Gain Error ◽  
Dc Gain

The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage ΔΣ modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based ΔΣ modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the CadenceTM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.

A 16.4 nW, Sub-1 V, Resistor-Less Voltage Reference with BJT Voltage Divider

2018 ◽  
Vol 27 (13) ◽  
pp. 1850206 ◽  
Author(s):  
Qingshan Yang ◽  
Peiqing Han ◽  
Niansong Mei ◽  
Zhaofeng Zhang
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Voltage Divider ◽  
Total Power ◽  
Cmos Process ◽  
Operating Voltage ◽  
Voltage Reference ◽  
Ultra Low Power ◽  
Silicon Area ◽  
Total Power Consumption

A 16.4[Formula: see text]nW, sub-1[Formula: see text]V voltage reference for ultra-low power low voltage applications is proposed. This design reduces the operating voltage to 0.8[Formula: see text]V by a BJT voltage divider and decreases the silicon area considerably by eliminating resistors. The PTAT and CTAT are based on SCM structures and a scaled-down [Formula: see text], respectively, to improve the process insensitivity. This work is fabricated in 0.18[Formula: see text][Formula: see text]m CMOS process with a total area of 0.0033[Formula: see text]mm2. Measured results show that it works properly for supply voltage from 0.8[Formula: see text]V to 2[Formula: see text]V. The reference voltage is 467.2[Formula: see text]mV with standard deviation ([Formula: see text]) being 12.2 mV and measured TC at best is 38.7[Formula: see text]ppm/[Formula: see text]C ranging from [Formula: see text]C to 60[Formula: see text]C. The total power consumption is 16.4[Formula: see text]nW under the minimum supply voltage at 27[Formula: see text]C.

scholarly journals Approximate Square Root Circuits with Low Latency and Power Dissipation

Electronics ◽  
2021 ◽  
Vol 11 (1) ◽  
pp. 46
Author(s):  
Duhwan Kim ◽  
Sunggu Lee
Keyword(s):  
Power Dissipation ◽  
Structural Similarity ◽  
Error Rates ◽  
Low Latency ◽  
Cmos Process ◽  
Square Root ◽  
Low Area ◽  
Image Contrast Enhancement ◽  
User Design ◽  
Power Delay Product

This paper proposes a series of approximate square root circuit designs with high accuracy, low latency, low area, and low power dissipation requirements. The proposed designs are constructed using an array of controlled add–subtract cell elements with both exact and approximate versions. The utility of the proposed designs are evaluated by utilizing them in an example image contrast enhancement application with demonstrably satisfactory results and large peak signal-to-noise ratios and structural similarity values. The accuracy and hardware characteristics of the proposed square root designs are also analyzed and compared with previously proposed state-of-the-art approximate square root designs. When applied to a 16-bit radicand (the number under the square root symbol), the proposed designs have the lowest error rates, normalized mean error distances, and mean relative error distances by at least 1.8x when compared to all previous methods using the same number of approximate cells. When the designs were synthesized using Synopsys Design Compiler with a 28 nm bulk CMOS process, the delay, area, power, and power-delay-product characteristics outperform all previous designs in all but a few cases. These results demonstrate that the proposed designs permit the use of a flexible range of approximate designs with varying accuracy and hardware overhead characteristics, and a suitable design can be selected based on the user design requirements.

scholarly journals A 0.8 V 0.23 nW 1.5 ns Full-Swing Pass-Transistor XOR Gate in 130 nm CMOS

2013 ◽  
Vol 2013 ◽  
pp. 1-6 ◽  
Author(s):  
Nabihah Ahmad ◽  
Rezaul Hasan
Keyword(s):  
Circuit Design ◽  
Power Dissipation ◽  
Low Voltage ◽  
Supply Voltage ◽  
Propagation Delay ◽  
Cmos Process ◽  
Xor Gate ◽  
Power Efficient ◽  
Pass Transistor ◽  
Full Swing

A power efficient circuit topology is proposed to implement a low-voltage CMOS 2-input pass-transistor XOR gate. This design aims to minimize power dissipation and reduce transistor count while at the same time reducing the propagation delay. The XOR gate utilizes six transistors to achieve a compact circuit design and was fabricated using the 130 nm IBM CMOS process. The performance of the XOR circuit was validated against other XOR gate designs through simulations using the same 130 nm CMOS process. The area of the core circuit is only about 56 sq · µm with 1.5659 ns propagation delay and 0.2312 nW power dissipation at 0.8 V supply voltage. The proposed six-transistor implementation thus compares favorably with other existing XOR gate designs.

scholarly journals Dynamic power dissipation of basic logic gates

2021 ◽  
Author(s):  
Katayoun Pourbahri
Keyword(s):  
Power Dissipation ◽  
Logic Gate ◽  
Load Condition ◽  
Order Relation ◽  
Logic Gates ◽  
Cmos Technology ◽  
Output Coupling ◽  
Basic Logic ◽  
Dynamic Power ◽  
Proposed Model

In this thesis, a model is proposed to estimate the dynamic power dissipation of CMOS logic gate that is loaded with identical logic gates. The proposed model is based on parsitic capacitance, input capacitance and input-to-output coupling capacitance of the gate. Also, model takes into account transistor width and has a second order relation with fanout. Using 0.13um CMOS technology and netlist (Cadence), basic logic gates are designed and loaded by identical basic logic gates. Basic logic gates dynamic power are simulated and compared with the calculated values of proposed model over a range of transistor sizes and capacitive load condition. The proposed model shows a good agreement with the simulated value of dynamic power dissipation of basic logic gates that are loaded by identical basic logic gates.

scholarly journals Low Voltage Full Swing FinFET Hybrid Full Adder

2019 ◽  
Vol 8 (2) ◽  
pp. 4253-4263
Keyword(s):  
Power Dissipation ◽  
Low Voltage ◽  
Average Power ◽  
Full Adder ◽  
Voltage Range ◽  
Lower Power ◽  
Low Power Dissipation ◽  
Power Delay Product ◽  
Full Swing ◽  
Cmos Implementation

In this research paper, CMOS and FinFET based hybrid Full Adders operating at low voltages with low power dissipation are proposed. The proposed CMOS based circuit is compared with few existing hybrid full adders in terms of average power dissipation and power-delay-product (PDP). The designed CMOS based hybrid adder achieves lower power dissipation and low PDP compared to other hybrid adders over a voltage range of 0.6V to 1V. The proposed CMOS implementation of hybrid full adder fails at 0.5V to produce full swing output. To solve this full swing problem, the proposed hybrid full adder is implemented using FinFETs which produce full output voltage, lower power and low PDP comparing with CMOS implementation. The circuits are designed with HSPICE tool in 32nm predictive technology model (PTM).

scholarly journals On Mixed PTL/Static Logic for Low-power and High-speed Circuits

VLSI Design ◽  
2001 ◽  
Vol 12 (3) ◽  
pp. 399-406 ◽  
Author(s):  
Geun Rae Cho ◽  
Tom Chen
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Logic Gates ◽  
Cmos Technology ◽  
Cmos Process ◽  
Test Cases ◽  
Static Structure ◽  
Average Delay ◽  
Power Delay Product ◽  
Static Logic

We present more evidence in a 0.25 μm CMOS technology that the pass-transistor logic (PTL) structure that mixes conventional PTL structure with static logic gates can achieve better performance and lower power consumption compared to conventional PTL structure. The goal is to use the static gates to perform both logic functions as well as buffering. Our experimental results demonstrate that the proposed mixed PTL structure beats pure static structure and conventional PTL in 9 out of 15 test cases for either delay or power consumption or both in a 0.25 μm CMOS process. The average delay, power consumption, and power-delay product of the proposed structure for 15 test cases are 10% to 20% better of than the pure static implementations and up to 50% better than the conventional PTL implementations.

scholarly journals Simple Scheme for the Implementation of Low Voltage Fully Differential Amplifiers without Output Common-Mode Feedback Network

2020 ◽  
Vol 10 (4) ◽  
pp. 34
Author(s):  
Mario Renteria-Pinon ◽  
Jaime Ramirez-Angulo ◽  
Alejandro Diaz-Sanchez
Keyword(s):  
Figure Of Merit ◽  
Low Voltage ◽  
Cmos Process ◽  
Large Signal ◽  
Simple Scheme ◽  
Common Mode ◽  
Differential Amplifiers ◽  
Fully Differential ◽  
Feedback Network ◽  
Strong Inversion

A simple scheme to implement class AB low-voltage fully differential amplifiers that do not require an output common-mode feedback network (CMFN) is introduced. It has a rail to rail output signal swing and high rejection of common-mode input signals. It operates in strong inversion with ±300 mV supplies in a 180 nm CMOS process. It uses an auxiliary amplifier that minimizes supply requirements by setting the op-amp input terminals very close to one of the rails and also serves as a common-mode feedback network to generate complementary output signals. The scheme is verified with simulation results of an amplifier that consumes 25 µW, has a gain-bandwidth product (GBW) of 16.1 MHz, slew rate (SR) of 8.4 V/µs, the small signal figure of merit (FOMSS) of 6.49 MHz*pF/µW, the large signal figure of merit (FOMLS) of 3.39 V/µs*pF/µW, and current efficiency (CE) of 2.03 in strong inversion, with a 10 pF load capacitance.

AN OPTIMIZED LOW POWER PIPELINE ANALOG-TO-DIGITAL CONVERTER FOR HIGH-SPEED WLAN APPLICATION

2014 ◽  
Vol 23 (05) ◽  
pp. 1450059 ◽  
Author(s):  
MAO YE ◽  
BIN WU ◽  
YONGXU ZHU ◽  
YUMEI ZHOU
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Dynamic Range ◽  
Cmos Process ◽  
Area Network ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Silicon Area ◽  
Analog To Digital

This paper presents the design and implementation of a 11-bit 160 MSPS analog-to-digital converter (ADC) for next generation super high-speed wireless local area network (WLAN) application. The ADC core consists of one front sample and hold stage and four cascades of 2.5 bit pipeline stages with opamp sharing between successive stages. To achieve low power dissipation at 1.2 V supply, a single stage symmetrical amplifier with double transimpedance gain-boosting amplifier is proposed. High speed on-chip reference buffer with replica source follower is also included for linearity performance. The ADC was fabricated in a standard 130-nm CMOS process and an occupied silicon area of 0.95 mm × 1.15 mm. Performance of 73 dB spurious-free-dynamic-range is measured at 160 MS/s with 1 Vpp input signal. The power dissipation of the analog core chip is only 50 mW from a 1.2 V supply.

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