scholarly journals Double-Gate Negative-Capacitance MOSFET With PZT Gate-Stack on Ultra Thin Body SOI: An Experimentally Calibrated Simulation Study of Device Performance

2016 ◽  
Vol 63 (12) ◽  
pp. 4678-4684 ◽  
Author(s):  
Ali Saeidi ◽  
Farzan Jazaeri ◽  
Igor Stolichnov ◽  
Adrian M. Ionescu
Keyword(s):  
Simulation Study ◽  
Thin Body ◽  
Device Performance ◽  
Negative Capacitance ◽  
Double Gate ◽  
Gate Stack ◽  
Calibrated Simulation

Ion implantation for low-resistive source/drain contacts in FinFET devices

2008 ◽  
Vol 1070 ◽  
Author(s):  
Mark J. H. van Dal ◽  
Ray Duffy ◽  
Bartek J. Pawlak ◽  
Nadine Collaert ◽  
Malgorzata Jurczak ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Doping Concentration ◽  
Silicon Crystal ◽  
Thin Body ◽  
Device Performance ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effect ◽  
A New Technique ◽  
Resistive Source

ABSTRACTFinFET is one of the leading candidates to replace the classical planar MOSFET for future CMOS technologies due to the double-gate configuration of the device leading to an intrinsically superior short channel effect (SCE) control. A major challenge for FinFETs is the increase in parasitic source-drain resistance (Rsd) as the fin width is scaled. As fins must be narrow in order to control SCEs, Rsd reduction is critical. This work will deal with the challenges faced in the use of ion implantation for the low-ohmic source-drain contacts. Firstly a new technique to characterize fin sidewall doping concentration will be introduced. We will have a closer look at the Rsd dependency upon fin width for different fin implant conditions and investigate how the implant conditions affect FinFET device performance. It will be shown that the cause of the device degradation upon fin width scaling is related to the fundamental issues of silicon crystal integrity in thin-body Si after amorphizing implant and recrystallization during source-drain activation.

SIMULATION STUDY ON THE ELECTRICAL PERFORMANCE OF EQUILIBRIUM THIN-BODY DOUBLE-GATE NANO-MOSFET

2015 ◽  
Vol 76 (1) ◽  
Author(s):  
Chek Yee Ooi ◽  
Lim Soo King
Keyword(s):  
Simulation Study ◽  
Model Simulation ◽  
Classical Model ◽  
Electron Velocity ◽  
Electrical Performance ◽  
Thin Body ◽  
Quantum Model ◽  
Double Gate ◽  
Electrical Characteristics ◽  
Nano Mosfet

This paper presents a numerical simulation study for electrical characteristics of double-gate (DG) nano-MOSFET at equilibrium thin-body condition. The electrical characteristics which are studied include subband energy (including unprimed and primed subbands), 2D electron density at 77K and 300K ambient temperatures, transmission coefficient, average electron velocity and ballistic current. The ranges of silicon body thickness TSi are 1.0 nm, 1.5 nm and 2.0 nm. The electron transport models used in simulation tool covered quantum model and classical model. Simulation output data are also compared with theoretical discussion.

Effect of Body Thickness on Device Performance of Graded Channel Tri-Metal Double Gate Stack Gate TFET

2020 ◽  
Author(s):  
Sudipta Ghosh ◽  
Supratim Kundu ◽  
Sourav Guha ◽  
Jui Ghosh ◽  
Prithviraj Pachal ◽  
...  
Keyword(s):  
Device Performance ◽  
Double Gate ◽  
Gate Stack
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