Ion implantation for low-resistive source/drain contacts in FinFET devices

2008 ◽  
Vol 1070 ◽  
Author(s):  
Mark J. H. van Dal ◽  
Ray Duffy ◽  
Bartek J. Pawlak ◽  
Nadine Collaert ◽  
Malgorzata Jurczak ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Doping Concentration ◽  
Silicon Crystal ◽  
Thin Body ◽  
Device Performance ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effect ◽  
A New Technique ◽  
Resistive Source

ABSTRACTFinFET is one of the leading candidates to replace the classical planar MOSFET for future CMOS technologies due to the double-gate configuration of the device leading to an intrinsically superior short channel effect (SCE) control. A major challenge for FinFETs is the increase in parasitic source-drain resistance (Rsd) as the fin width is scaled. As fins must be narrow in order to control SCEs, Rsd reduction is critical. This work will deal with the challenges faced in the use of ion implantation for the low-ohmic source-drain contacts. Firstly a new technique to characterize fin sidewall doping concentration will be introduced. We will have a closer look at the Rsd dependency upon fin width for different fin implant conditions and investigate how the implant conditions affect FinFET device performance. It will be shown that the cause of the device degradation upon fin width scaling is related to the fundamental issues of silicon crystal integrity in thin-body Si after amorphizing implant and recrystallization during source-drain activation.

Effects of ultra-thin Si-fin body widths upon SOI PMOS FinFETs

2018 ◽  
Vol 32 (15) ◽  
pp. 1850157 ◽  
Author(s):  
Yue-Gie Liaw ◽  
Chii-Wen Chen ◽  
Wen-Shiang Liao ◽  
Mu-Chun Wang ◽  
Xuecheng Zou
Keyword(s):  
Gate Oxide ◽  
Silicon On Insulator ◽  
Double Gate ◽  
Current Crowding ◽  
Crowding Effect ◽  
Short Channel ◽  
Channel Mobility ◽  
Channel Effect ◽  
193 Nm ◽  
Dry Etch

Nano-node tri-gate FinFET devices have been developed after integrating a 14 Å nitrided gate oxide upon the silicon-on-insulator (SOI) wafers established on an advanced CMOS logic platform. These vertical double gate (FinFET) devices with ultra-thin silicon fin (Si-fin) widths ranging from 27 nm to 17 nm and gate length down to 30 nm have been successfully developed with a 193 nm scanner lithography tool. Combining the cobalt fully silicidation and the CESL strain technology beneficial for PMOS FinFETs was incorporated into this work. Detailed analyses of [Formula: see text]–[Formula: see text] characteristics, threshold voltage [Formula: see text], and drain-induced barrier lowering (DIBL) illustrate that the thinnest 17 nm Si-fin width FinFET exhibits the best gate controllability due to its better suppression of short channel effect (SCE). However, higher source/drain resistance [Formula: see text], channel mobility degradation due to dry etch steps, or “current crowding effect” will slightly limit its transconductance [Formula: see text] and drive current.

TCAD Modeling and Simulation of Sub-100nm Gate Length Silicon and GaN based SOI MOSFETs

2006 ◽  
Vol 913 ◽  
Author(s):  
Lei Ma ◽  
Yawei Jin ◽  
Chang Zeng ◽  
Krishnanshu Dandu ◽  
Mark Johnson ◽  
...  
Keyword(s):  
Cylindrical Channel ◽  
Device Performance ◽  
Gate Length ◽  
Short Channel ◽  
Promising Candidate ◽  
Fully Depleted ◽  
Triangular Channel ◽  
Channel Effect ◽  
Comparable Performance ◽  
Silicon Based

AbstractSub-100nm gate length silicon and GaN based SOI n-type MOSFET are modeled and simulated using ISE-TCAD (now synopsys_sentaurus). Several silicon SOI structures such as planar fully depleted SOI, FinFET, Tri-Gate MOSFET, cylindrical channel (OMFET) and triangular channel MOSFETs have been studied to compare the structure dependence of the device performance. Silicon and GaN as channel materials are also compared for these different SOI structures for projecting the device performance for very short channel SOI MOSFETs. Our study shows that for sub-100nm gate length, GaN based transistors have better Ion/Ioff ratio and higher small signal transconductance than silicon based transistors. And GaN and Si based devices have comparable performance such as sub-threshold slope and threshold roll off, etc. However for sub 20nm gate length, simulation shows that while it is not satisfying for silicon based device for digital applications, GaN based transistors with lower off state leakage current, less short channel effect than Silicon based transistors are still good candidates for digital applications . The TCAD study shows that GaN could be a promising candidate for making very short channel device as the GaN processing technology is advancing.

Experimental evidence of mobility enhancement in short-channel ultra-thin body double-gate MOSFETs by magnetoresistance technique

2007 ◽  
Vol 51 (11-12) ◽  
pp. 1494-1499 ◽  
Author(s):  
W. Chaisantikulwat ◽  
M. Mouis ◽  
G. Ghibaudo ◽  
S. Cristoloveanu ◽  
J. Widiez ◽  
...  
Keyword(s):  
Experimental Evidence ◽  
Thin Body ◽  
Double Gate ◽  
Short Channel

Effects of Compositional Segregation and Short Channel on Threshold Voltage of nMOSFET

1997 ◽  
Vol 490 ◽  
Author(s):  
Julie Y. H. Lee ◽  
Tom C. H. Lee ◽  
Mike Embry ◽  
Keenan Evans ◽  
Dan Koch ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Doping Concentration ◽  
Channel Length ◽  
Drift Diffusion ◽  
Short Channel ◽  
Short Channel Effect ◽  
Dopant Segregation ◽  
Channel Effect ◽  
Substrate Doping ◽  
Compositional Segregation

ABSTRACTThis study calculates the threshold voltage (VT) roll-off behavior caused by short channel effect (SCE) as a result of scaling and the reverse short-channel effect (RSCE) due to B segregation around source and drain junctions by using the 2D device simulator - SILVACO™-ATLAS. The simulation results are comparable with the experimental data. It suggests that the drift diffusion physics can predict SCE and RSCE very well to sub-0.25μ Si n-MOSFET devices. The modeling results indicate the VT roll off at shorter channel length for devices with higher substrate doping concentration. VT increases if the local p-dopant segregation exists around the source and drain junction. It is observed that RSCE is more significant for devices with lower substrate doping concentration and shorter channel length.

scholarly journals Effect of Oxide Thickness on GaN-based Double Gate MOSFETs

2020 ◽  
Vol 16 (2) ◽  
Author(s):  
Safayet Ahmed ◽  
Md. Tanvir Hasan
Keyword(s):  
Oxide Thickness ◽  
Device Performance ◽  
Gate Length ◽  
Double Gate ◽  
Short Channel Effects ◽  
Subthreshold Slope ◽  
Short Channel ◽  
Power Switching ◽  
Switching Device ◽  
Channel Effects

The effect of oxide thickness (EOT) on GaN-based double gate (DG) MOSFETs have been explored for low power switching device. The gate length (LG) of 8 nm with 4 nm underlap is considered. The device is turned off and on for gate voltage (VGS) of 0 V and 1 V, respectively. The effective oxide thickness (EOT) is varied from 1 nm to 0.5 nm and the device performance is evaluated. For EOT = 0.5 nm, the OFF-state current (IOFF), subthreshold slope (SS) and drain induced barrier lowering (DIBL) are obtained 2.97×10-8 A/μm, 69.67 mV/dec and 21.753 mV/V, respectively. These results indicate that, it is possible to minimize short channel effects (SCEs) by using smaller value of EOT.

Gate length scaling optimization of FinFETs

2018 ◽  
Vol 32 (14) ◽  
pp. 1850176 ◽  
Author(s):  
Shoumian Chen ◽  
Enming Shang ◽  
Shaojian Hu
Keyword(s):  
Work Function ◽  
Leakage Current ◽  
Performance Optimization ◽  
Device Performance ◽  
Optimization Approach ◽  
Gate Length ◽  
Short Channel ◽  
Drive Current ◽  
Channel Effect ◽  
Length Scaling

This paper introduces a device performance optimization approach for the FinFET through optimization of the gate length. As a result of reducing the gate length, the leakage current (I[Formula: see text]) increases, and consequently, the stress along the channel enhances which leads to an increase in the drive current (I[Formula: see text]) of the PMOS. In order to sustain I[Formula: see text], work function is adjusted to offset the effect of the increased stress. Changing the gate length of the transistor yields different drive currents when the leakage current is fixed by adjusting the work function. For a given device, an optimal gate length is found to provide the highest drive current. As an example, for a standard performance device with I[Formula: see text] = 1 nA/um, the best performance I[Formula: see text] = 856 uA/um is at L = 34 nm for 14 nm FinFET and I[Formula: see text] = 1130 uA/um at L = 21 nm for 7 nm FinFET. A 7 nm FinFET will exhibit performance boost of 32% comparing with 14 nm FinFET. However, applying the same method to a 5 nm FinFET, the performance boosting is out of expectance comparing to the 7 nm FinFET, which is due to the severe short-channel-effect and the exhausted channel stress in the FinFET.

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