A Novel High-Performance Planar InAs/GaSb Face-Tunneling FET With Implanted Drain for Leakage Current Reduction

2021 ◽  
Vol 68 (3) ◽  
pp. 1313-1317
Author(s):  
Zhijun Lyu ◽  
Hongliang Lv ◽  
Yuming Zhang ◽  
Yimen Zhang ◽  
Yi Zhu ◽  
...  
Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 312 ◽  
Author(s):  
Woo-Young Choi ◽  
Min-Kwon Yang

The conventional single-phase quasi-Z-source (QZS) inverter has a high leakage current as it is connected to the grid. To address this problem, this paper proposes a transformerless QZS inverter, which can reduce the leakage current for single-phase grid-tied applications. The proposed inverter effectively alleviates the leakage current problem by removing high-frequency components for the common-mode voltage. The operation principle of the proposed inverter is described together with its control strategy. A control scheme is presented for regulating the DC-link voltage and the grid current. A 1.0 kW prototype inverter was designed and tested to verify the performance of the proposed inverter. Silicon carbide (SiC) power devices were applied to the proposed inverter to increase the power efficiency. The experimental results showed that the proposed inverter achieved high performance for leakage current reduction and power efficiency improvement.


2021 ◽  
Vol 34 (2) ◽  
pp. 259-280
Author(s):  
Sankit Kassa ◽  
Neeraj Misra ◽  
Rajendra Nagaria

Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN (FORced stack sleep TRANsistor), which decreases the leakage power efficiency in the CMOS-based circuit outline in VLSI domain. FORTRAN approach reduces leakage current in both active as well as standby modes of operation. Furthermore, it is not time intensive when the circuit goes from active mode to standby mode and vice-versa. To validate the proposed design approach, experiments are conducted in the Tanner EDA tool of mentor graphics bundle on projected circuit designs for the full adder, a chain of 4-inverters, and 4- bit multiplier designs utilizing 180nm, 130nm, and 90nm TSMC technology node. The outcomes obtained show the result of a 95-98% vital reduction in leakage power as well as a 15-20% reduction in dynamic power with a minor increase in delay. The result outcomes are compared for accuracy with the notable design approaches that are accessible for both active and standby modes of operation.


2018 ◽  
Vol 28 (8) ◽  
pp. 440-444
Author(s):  
Kwang-Jin Lee ◽  
◽  
Doyeon Kim ◽  
Duck-Kyun Choi ◽  
Woo-Byoung Kim

2021 ◽  
Vol 57 (15) ◽  
pp. 1907-1910
Author(s):  
Dapeng Liu ◽  
Yiwei Zhao ◽  
Qianqian Shi ◽  
Shilei Dai ◽  
Li Tian ◽  
...  

A solid-state hybrid electrolyte dielectric film was designed for leakage current reduction, synaptic simulation and neuromorphic computing systems.


Author(s):  
Xiaonan Zhu ◽  
Hongliang Wang ◽  
Wenyuan Zhang ◽  
Hanzhe Wang ◽  
Xiaojun Deng ◽  
...  

2013 ◽  
Vol 1538 ◽  
pp. 291-302
Author(s):  
Edward Yi Chang ◽  
Hai-Dang Trinh ◽  
Yueh-Chin Lin ◽  
Hiroshi Iwai ◽  
Yen-Ku Lin

ABSTRACTIII-V compounds such as InGaAs, InAs, InSb have great potential for future low power high speed devices (such as MOSFETs, QWFETs, TFETs and NWFETs) application due to their high carrier mobility and drift velocity. The development of good quality high k gate oxide as well as high k/III-V interfaces is prerequisite to realize high performance working devices. Besides, the downscaling of the gate oxide into sub-nanometer while maintaining appropriate low gate leakage current is also needed. The lack of high quality III-V native oxides has obstructed the development of implementing III-V based devices on Si template. In this presentation, we will discuss our efforts to improve high k/III-V interfaces as well as high k oxide quality by using chemical cleaning methods including chemical solutions, precursors and high temperature gas treatments. The electrical properties of high k/InSb, InGaAs, InSb structures and their dependence on the thermal processes are also discussed. Finally, we will present the downscaling of the gate oxide into sub-nanometer scale while maintaining low leakage current and a good high k/III-V interface quality.


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