A 2.56-GHz SEU Radiation Hard $LC$ -Tank VCO for High-Speed Communication Links in 65-nm CMOS Technology

This paper presents a novel scalable physical implementation method for high-speed Triple Modular Redundant (TMR) digital integrated circuits in radiation-hard designs. The implementation uses a distributed placement strategy compared to a commonly used bulk 3-bank constraining method. TMR netlist information is used to optimally constrain the placement of both sequential cells and combinational cells. This approach significantly reduces routing complexity, net lengths and dynamic power consumption with more than 60% and 20% respectively. The technique was simulated in a 65 nm Complementary Metal-Oxide Semiconductor (CMOS) technology.

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A DUAL MODULATION PULSE POSITION MODULATION APPROACH IN 130NM CMOS TECHNOLOGY FOR TIME BASED SERIAL COMMUNICATION LINKS

Journal of Advanced Engineering Trends ◽

10.21608/jaet.2020.73033 ◽

2020 ◽

Vol 38 (2) ◽

pp. 97-106

Author(s):

Mostafa Salah Rashdan ◽

Nesma M. Sobhy ◽

Ahmed El-Sawy

Keyword(s):

Serial Communication ◽

Cmos Technology ◽

Pulse Position Modulation ◽

Communication Links

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Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

Circulation in Computer Science ◽

10.22632/ccs-2017-251-50 ◽

2017 ◽

Vol 2 (2) ◽

pp. 15-19 ◽

Cited By ~ 3

Author(s):

Md. Saud Al Faisal ◽

Md. Rokib Hasan ◽

Marwan Hossain ◽

Mohammad Saiful Islam

Keyword(s):

High Speed ◽

Field Effect Transistors ◽

Cmos Technology ◽

Channel Length ◽

Capacitive Coupling ◽

Oxide Semiconductor ◽

Double Gate ◽

Short Channel ◽

Channel Effects ◽

Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

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The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

Applied Sciences ◽

10.3390/app11010429 ◽

2021 ◽

Vol 11 (1) ◽

pp. 429

Author(s):

Min-Su Kim ◽

Youngoo Yang ◽

Hyungmo Koo ◽

Hansik Oh

Keyword(s):

Integrated Circuits ◽

Embedded System ◽

Low Power ◽

High Speed ◽

Cmos Technology ◽

Clock Frequency ◽

Clock Generation ◽

Allocation Method ◽

Evaluation Board ◽

28 Nm

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

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Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽

10.3390/mi12050551 ◽

2021 ◽

Vol 12 (5) ◽

pp. 551

Author(s):

Zhongjian Bian ◽

Xiaofeng Hong ◽

Yanan Guo ◽

Lirida Naviner ◽

Wei Ge ◽

...

Keyword(s):

Nonvolatile Memory ◽

High Speed ◽

Low Voltage ◽

Supply Voltage ◽

Random Access ◽

Magnetic Tunnel Junction ◽

Complementary Metal Oxide Semiconductor ◽

Current Mode ◽

Cmos Technology ◽

Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

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A manufacturable 0.30 μm gate CMOS technology for high speed microprocessors

1996 Symposium on VLSI Technology. Digest of Technical Papers ◽

10.1109/vlsit.1996.507857 ◽

2002 ◽

Cited By ~ 1

Author(s):

A. Appel ◽

S. Crank ◽

Y. Kim ◽

C. Scharrer ◽

D. Spratt ◽

...

Keyword(s):

High Speed ◽

Cmos Technology

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Novel Manchester-Based Multilevel Signaling for High-Speed Optical Communication Systems

Journal of Optical Communications ◽

10.1515/joc-2018-0139 ◽

2019 ◽

Vol 0 (0) ◽

Cited By ~ 1

Author(s):

Festus Idowu Oluwajobi ◽

Nguyen Dong-Nhat ◽

Amin Malekmohammadi

Keyword(s):

Communication Systems ◽

High Speed ◽

Chromatic Dispersion ◽

Optical Fiber Communication ◽

Pulse Amplitude ◽

Calculation Model ◽

Fiber Communication ◽

Receiver Sensitivity ◽

Communication Links ◽

Dispersion Tolerance

AbstractIn this paper, the performance of a novel multilevel signaling based on Manchester code namely four-level Manchester Coding (4-MC) technique is investigated for next generation high-speed optical fiber communication links. The performance of 4-MC is studied and compared with conventional Manchester modulation and four-level pulse amplitude modulation (4-PAM) formats in terms of receiver sensitivity, spectral efficiency and dispersion tolerance at the bit rate of 40 Gb/s. The bit error rate (BER) calculation model for the proposed multilevel scheme has also been developed. The calculated receiver sensitivity and the chromatic dispersion tolerance at the BER of 10–9 of the proposed scheme are −22 dBm and 67.5 ps/nm, respectively. It is observed that, 4-MC scheme is superior in comparison to 4-PAM by 3.5 dB in terms of receiver sensitivity in back-to-back scenario. Therefore, the proposed scheme can be considered as an alternative to current 4-PAM system.

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