A 25.9-GHz voltage-controlled oscillator fabricated in a CMOS process

2002 ◽  
Author(s):  
C.-M. Hung ◽  
L. Shi ◽  
I. Laguado ◽  
K.K. O
Keyword(s):  
Cmos Process ◽  
Voltage Controlled Oscillator

scholarly journals An Ultra-Low-Power K-Band 22.2 GHz-to-26.9 GHz Current-Reuse VCO Using Dynamic Back-Gate-Biasing Technique

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 889
Author(s):  
Xiaoying Deng ◽  
Peiqi Tan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Tuning Range ◽  
Frequency Tuning ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Back Gate ◽  
Ultra Low Power ◽  
Current Reuse ◽  
K Band

An ultra-low-power K-band LC-VCO (voltage-controlled oscillator) with a wide tuning range is proposed in this paper. Based on the current-reuse topology, a dynamic back-gate-biasing technique is utilized to reduce power consumption and increase tuning range. With this technique, small dimension cross-coupled pairs are allowed, reducing parasitic capacitors and power consumption. Implemented in SMIC 55 nm 1P7M CMOS process, the proposed VCO achieves a frequency tuning range of 19.1% from 22.2 GHz to 26.9 GHz, consuming only 1.9 mW–2.1 mW from 1.2 V supply and occupying a core area of 0.043 mm2. The phase noise ranges from −107.1 dBC/HZ to −101.9 dBc/Hz at 1 MHz offset over the whole tuning range, while the total harmonic distortion (THD) and output power achieve −40.6 dB and −2.9 dBm, respectively.

scholarly journals A 1.55-to-32-Gb/s Four-Lane Transmitter with 3-Tap Feed Forward Equalizer and Shared PLL in 28-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1873
Author(s):  
Chen Cai ◽  
Xuqiang Zheng ◽  
Yong Chen ◽  
Danyu Wu ◽  
Jian Luan ◽  
...  
Keyword(s):  
Data Transmission ◽  
High Speed ◽  
Data Rate ◽  
Quality Data ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Feed Forward ◽  
Fully Integrated ◽  
Output Driver ◽  
28 Nm

This paper presents a fully integrated physical layer (PHY) transmitter (TX) suiting for multiple industrial protocols and compatible with different protocol versions. Targeting a wide operating range, the LC-based phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) was integrated to provide the low jitter clock. Each lane with a configurable serialization scheme was adapted to adjust the data rate flexibly. To achieve high-speed data transmission, several bandwidth-extended techniques were introduced, and an optimized output driver with a 3-tap feed-forward equalizer (FFE) was proposed to accomplish high-quality data transmission and equalization. The TX prototype was fabricated in a 28-nm CMOS process, and a single-lane TX only occupied an active area of 0.048 mm2. The shared PLL and clock distribution circuits occupied an area of 0.54 mm2. The proposed PLL can support a tuning range that covers 6.2 to 16 GHz. Each lane's data rate ranged from 1.55 to 32 Gb/s, and the energy efficiency is 1.89 pJ/bit/lane at a 32-Gb/s data rate and can tune an equalization up to 10 dB.

Design and analysis of a low noise CMOS charge pump phase locked loop circuit

2021 ◽  
pp. 2140002
Author(s):  
Yanbo Chen ◽  
Shubin Zhang
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Low Noise ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Output Frequency ◽  
Power Supply Voltage ◽  
Supply Noise

Phase Locked Loop (PLL) circuit plays an important part in electronic communication system in providing high-frequency clock, recovering the clock from data signal and so on. The performance of PLL affects the whole system. As the frequency of PLL increases, designing a PLL circuit with lower jitter and phase noise becomes a big challenge. To suppress the phase noise, the optimization of Voltage Controlled Oscillator (VCO) is very important. As the power supply voltage degrades, the VCO becomes more sensitive to supply noise. In this work, a three-stage feedforward ring VCO (FRVCO) is designed and analyzed to increase the output frequency. A novel supply-noise sensing (SNS) circuit is proposed to suppress the supply noise’s influence on output frequency. Based on these, a 1.2 V 2 GHz PLL circuit is implemented in 110 nm CMOS process. The phase noise of this CMOS charge pump (CP) PLL is 117 dBc/Hz@1 MHz from test results which proves it works successfully in suppressing phase noise.

Ground-Adjustable Inductor for Wide-Tuning VCO Design

2012 ◽  
Vol 256-259 ◽  
pp. 2373-2378
Author(s):  
Wu Shiung Feng ◽  
Chin I Yeh ◽  
Ho Hsin Li ◽  
Cheng Ming Tsao
Keyword(s):  
Power Consumption ◽  
Tuning Range ◽  
Supply Voltage ◽  
Wide Band ◽  
Ultra Wide Band ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Wide Tuning Range ◽  
Chip Area ◽  
Ground Plate

A wide-tuning range voltage-controlled oscillator (VCO) with adjustable ground-plate inductor for ultra-wide band (UWB) application is presented in this paper. The VCO was implemented by standard 90nm CMOS process at 1.2V supply voltage and power consumption of 6mW. The tuning range from 13.3 GHz to 15.6 GHz with phase noise between -99.98 and -115dBc/Hz@1MHz is obtained. The output power is around -8.7 to -9.6dBm and chip area of 0.77x0.62mm2.

A Scalable Millimetre-Wave Differential CMOS Cross-Coupled VCO for Automotive Radar Application

2018 ◽  
Vol 27 (10) ◽  
pp. 1850158 ◽  
Author(s):  
Rekha Yadav ◽  
Pawan Kumar Dahiya ◽  
Rajesh Mishra
Keyword(s):  
Phase Noise ◽  
Oxide Semiconductor ◽  
Control Voltage ◽  
Cmos Process ◽  
Operating Voltage ◽  
Voltage Controlled Oscillator ◽  
Automotive Radar ◽  
Millimetre Wave ◽  
The Impact ◽  
Lc Vco

In this paper, a novel method to realize LC Voltage-Controlled-Oscillator (LC-VCO) operating at 76.2–76.7[Formula: see text]GHz frequency band for microwave RFIC component is presented. The model of cross-coupled differential LC-VCO is designed in 45[Formula: see text]nm technology using Complementary Metal Oxide Semiconductor (CMOS) process for Frequency Modulated Carrier Wave (FMCW) automotive radar sensors and RF transceivers application. The impact of VDD, control voltage and temperature variation on frequency shift, phase noise, and output power has been analyzed to optimize the trade-off between frequency, phase noise, and power requirement. The results depict that LC-VCO dissipates 10.45[Formula: see text]mW power at an operating voltage of 1.5[Formula: see text]V. The phase noise has been observed to be [Formula: see text]90[Formula: see text]dBc/Hz at 1[Formula: see text]MHz offset at 76[Formula: see text]GHz carrier frequency. The estimated layout area of IC is [Formula: see text]m2. The result shows the edge of the design over existing techniques.

A 2.3 mW Multi-Frequency Clock Generator with −137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology

2019 ◽  
Vol 29 (08) ◽  
pp. 2050130 ◽  
Author(s):  
Jagdeep Kaur Sahani ◽  
Anil Singh ◽  
Alpana Agarwal
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Dead Zone ◽  
Dynamic Logic ◽  
Cmos Technology ◽  
Control Voltage ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Cmos Inverter ◽  
Digital Cmos

A fast phase frequency detector (PFD) and low gain low phase noise voltage-controlled oscillator (VCO)-based phase-locked loop (PLL) design are presented in this paper. PLL works in the frequency range of 0.025–1.6[Formula: see text]GHz, targeting various SoC applications. The proposed PFD, designed using CMOS dynamic logic, is fast and improves the locking time, dead zone and blind zone in the PLL. The standard CMOS inverter gate-based pseudo differential VCO is used in the PLL. Also, CMOS inverter is used as variable capacitor to tune the frequency of VCO with control voltage. The proposed PLL is designed in a 180[Formula: see text]nm CMOS process with supply voltage of 1.8[Formula: see text]V. The phase noise of VCO is [Formula: see text][Formula: see text]dBc/Hz at an offset frequency of 100[Formula: see text]MHz. The reference clock of 25[Formula: see text]MHz synthesizes the output clock of 1.6[Formula: see text]GHz with rms jitter of 0.642[Formula: see text]ps.

scholarly journals Integrated VCOs for Medical Implant Transceivers

VLSI Design ◽  
2008 ◽  
Vol 2008 ◽  
pp. 1-10 ◽  
Author(s):  
Ahmet Tekin ◽  
Mehmet R. Yuce ◽  
Wentai Liu
Keyword(s):  
Data Transfer ◽  
Supply Voltage ◽  
Low Frequency ◽  
Federal Communication Commission ◽  
Implantable Devices ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Medical Implant ◽  
Shift Keying ◽  
Lc Tank

The 402–405 MHz medical implant communication service (MICS) band has recently been allocated by the US Federal Communication Commission (FCC) with the potential to replace the low-frequency inductive coupling techniques in implantable devices. This band was particularly chosen to provide full-integration, low-power, faster data transfer, and longer communication range. This paper investigates the design of a voltage-controlled oscillator (VCO) that will be an essential building block of such wireless implantable devices operating in the MICS service band. Three different integrated quadrature VCOs that meet the requirements of the MICS standard are designed in 0.18 μm TSMC CMOS process to propose an optimum choice. Their performances in terms of power consumption, die area, linearity, and phase noise are compared. The fabricated VCOs are a four-stage differential ring VCO, an LC tank VCO directly loaded with a poly-phase filter, and an 800 MHz LC tank VCO with a high-frequency master-slave divider. All three architectures target a VCO gain of Kvco = 15 MHz/V with 3 calibration control and 2 frequency-shift keying (FSK) control signals and are designed for 1.5 V supply voltage in a 0.18-μm standard CMOS process.

A 2.6-mW 106-GHz transmission-line-based voltage-controlled oscillator integrated in a 65-nm CMOS process

2011 ◽  
Author(s):  
Uroschanit Yodprasit ◽  
Mizuki Motoyoshi ◽  
Ryuichi Fujimoto ◽  
Kyoya Takano ◽  
Minoru Fujishima
Keyword(s):  
Transmission Line ◽  
Cmos Process ◽  
Voltage Controlled Oscillator

VCO-BASED CONTINUOUS-TIME SIGMA DELTA ADC BASED ON A DUAL-VCO-QUANTIZER-LOOP STRUCTURE

2013 ◽  
Vol 22 (09) ◽  
pp. 1340013 ◽  
Author(s):  
Z. T. XU ◽  
X. L. ZHANG ◽  
J. Z. CHEN ◽  
S. G. HU ◽  
Q. YU ◽  
...  
Keyword(s):  
Continuous Time ◽  
Signal To Noise Ratio ◽  
Quantization Noise ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Loop Structure ◽  
Signal To Noise ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Sigma Delta Adc

This paper explores a continuous time (CT) sigma delta (ΣΔ) analog-to-digital converter (ADC) based on a dual-voltage-controlled oscillator (VCO)-quantizer-loop structure. A third-order filter is adopted to reduce quantization noise and VCO nonlinearity. Even-order harmonics of VCO are significantly reduced by the proposed dual-VCO-quantizer-loop structure. The prototype with 10 MHz bandwidth and 400 MHz clock rate is designed using a 0.18 μm RF CMOS process. Simulation results show that the signal-to-noise ratio and signal-to-noise distortion ratio (SNDR) are 76.9 and 76 dB, respectively, consuming 37 mA at 1.8 V. The key module of the ADC, which is a 4-bit VCO-based quantizer, can convert the voltage signal into a frequency signal and quantize the corresponding frequency to thermometer codes at 400 MS/s.

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