A Low-Voltage and Label-Free Impedance-Based Miniaturized CMOS Biosensor for DNA Detection

2014 ◽  
Vol 67 (1) ◽  
Author(s):  
Vinny Lam Siu Fan ◽  
Wong How Hwan ◽  
Yusmeeraz Yusof
Keyword(s):  
Dynamic Range ◽  
Low Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Label Free ◽  
Fully Integrated ◽  
Technology Process ◽  
Common Gate ◽  
Study Designs

This study designs a low-voltage, label-free and fully integrated impedance-based biosensor using standard complementary metal oxide semiconductor (CMOS) technology to compute both capacitance and resistance of the electrode-electrolyte interface. The proposed biosensor circuit is composed of a common-gate transimpedance amplifier (CG-TIA) with two quadrature phase Gilbert cell double-balanced mixers and finally integrated with microelectrode using 0.18 µm Silterra CMOS technology process. The output value of the readout circuit was used to estimate the magnitude and phase of the measured admittance. The developed CG-TIA can achieve a gain of 88.6 dB up to a frequency of 50 MHz. The overall dynamic range was approximately 116 dB. 

Design of Fully Integrated Impedimetric CMOS Biosensor for DNA Detection

2014 ◽  
Vol 925 ◽  
pp. 524-528
Author(s):  
Vinny Lam Siu Fan ◽  
Yusmeeraz Binti Yusof
Keyword(s):  
Dynamic Range ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
High Gain ◽  
Oxide Semiconductor ◽  
Impedance Change ◽  
Readout Circuit ◽  
Label Free ◽  
Fully Integrated

This paper described a label-free and fully integrated impedimetric biosensor using standard Complementary Metal Oxide Semiconductor (CMOS) technology to measure both capacitance and resistance of the electrode-electrolyte interface. Conventional impedance biosensors usually use bulky and expensive instruments to monitor the impedance change. This paper demonstrates a low power, high gain and low cost impedance readout circuit design for detecting the biomolecular interactions of deoxyribonucleic acid (DNA) strands at the electrode surface. The proposed biosensor circuit is composed of a transimpedance amplifier (TIA) with two quadrature phase mixers and finally integrated with 5μm x 5μm microelectrode based on 0.18μm Silterra CMOS technology process with 1.8V supply. The output value of the readout circuit is used to estimate the amplitude and phase of the measured admittance. The developed TIA can achieve a gain of 88.6dB up to a frequency of 50MHz. It also has very good linearity up to 2.7mA and the overall dynamic range is approximately 90dB.

scholarly journals A Fully-Integrated 180 nm CMOS 1.2 V Low-Dropout Regulator for Low-Power Portable Applications

Electronics ◽  
2021 ◽  
Vol 10 (17) ◽  
pp. 2108
Author(s):  
Jorge Pérez-Bailón ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Low Voltage ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
High Gain ◽  
Oxide Semiconductor ◽  
Fully Integrated ◽  
Low Voltage Operation ◽  
Error Amplifier ◽  
Ldo Regulator

This paper presents the design and postlayout simulation results of a capacitor-less low dropout (LDO) regulator fully integrated in a low-cost standard 180 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology which regulates the output voltage at 1.2 V from a 3.3 to 1.3 V battery over a –40 to 120°C temperature range. To meet with the constraints of system-on-chip (SoC) battery-operated devices, ultralow power (Iq = 8.6 µA) and minimum area consumption (0.109 mm2) are maintained, including a reference voltage Vref = 0.4 V. It uses a high-gain dynamically biased folded-based error amplifier topology optimized for low-voltage operation that achieves an enhanced regulation-fast transient performance trade-off.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

scholarly journals A 1 GS/s 12-Bit Pipelined/SAR Hybrid ADC in 40 nm CMOS Technology

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 375
Author(s):  
Jianwen Li ◽  
Xuan Guo ◽  
Jian Luan ◽  
Danyu Wu ◽  
Lei Zhou ◽  
...  
Keyword(s):  
Successive Approximation ◽  
Dynamic Range ◽  
Complementary Metal Oxide Semiconductor ◽  
Wide Band ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Least Significant Bit ◽  
Analog To Digital ◽  
Successive Approximation Register ◽  
Adaptive Power

A 1 GS/s 12-bit pipelined/successive-approximation-register (pipelined/SAR) hybrid analog-to-digital converter (ADC) is presented in this paper, where the five most significant bits are resolved by two cascading 2.5-bit multiplying digital-to-analog converters, and the eight least significant bits are determined by a two-channel time-interleaved successive-approximation-register (TI-SAR) quantizer. An integrated input buffer and an operational amplifier with improved voltage efficiency at 1.8 V are adopted to achieve high-linearity stably in wide band for 1 GS/s. By designing a 500 MS/s 8-bit SAR quantizer at 1 V, the number of required interleaved channels is minimized to simplify the complexity and an adaptive power/ground is used to compensate the common-mode mismatch between the blocks in different power supply voltages. The offset and gain mismatches due to the TI-SAR quantizer are compensated by a calibration scheme based on virtually-interleaved channels. This ADC is fabricated in a 40 nm complementary metal-oxide-semiconductor (CMOS) technology, and it achieves a signal-to-noise-and-distortion ratio (SNDR) of 58.2 dB and a spurious free dynamic range (SFDR) of 72 dB with a 69 MHz input tone. When the input frequency increases to 1814 MHz in the fourth Nyquist zone, it can maintain an SNDR of 55.3 dB and an SFDR of 64 dB. The differential and integral nonlinearities are −0.94/+0.85 least significant bit (LSB) and −3.4/+3.9 LSB, respectively. The core ADC consumes 94 mW, occupies an active area of 0.47 mm × 0.25 mm. The Walden figure of merit reaches 0.14 pJ/step with a Nyquist input.

Complementary metal oxide semiconductor compatible high-voltage transistors

1987 ◽  
Vol 65 (8) ◽  
pp. 1003-1008
Author(s):  
P. Kempf ◽  
R. Hadaway ◽  
J. Kolk
Keyword(s):  
Metal Oxide ◽  
High Voltage ◽  
Process Model ◽  
Low Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Electrical Measurements ◽  
Cmos Transistors

The purpose of this work was to study the implementation of high-voltage transistors using standard 3–5 μm complementary metal oxide semiconductor (CMOS) technology with a minimum of additional photolithographic or implant steps. A fabrication process was designed to accommodate a variety of high-voltage transistors with greater than 450 V breakdown voltage and low-voltage CMOS. Extensive use was made of a two-dimensional device model and a one-dimensional process model to determine suitable process parameters. The necessary conditions to produce a high-voltage double-diffused metal oxide semiconductor (DMOS) structure, as well as both n-well and p-well regions for CMOS transistors, and a thick gate oxide required to sustain the full blocking voltage were the main determinants of the process flow. Lateral DMOS (LDMOS), vertical DMOS (VDMOS), conductivity modulated FET (COMFET), and MOS triac (TRIMOS) devices were fabricated on the same chip as standard CMOS transistors using the developed fabrication sequence. This paper includes the results of the process modelling, device design, and electrical measurements.

scholarly journals Fully Integrated Low-Ripple Switched-Capacitor DC–DC Converter with Parallel Low-Dropout Regulator

Electronics ◽  
2019 ◽  
Vol 8 (1) ◽  
pp. 98 ◽  
Author(s):  
Jeong-Yun Lee ◽  
Gwang-Sub Kim ◽  
Kwang-Il Oh ◽  
Donghyun Baek
Keyword(s):  
Transient Response ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Switched Capacitor ◽  
Wearable Electronics ◽  
Power Sources ◽  
Fully Integrated ◽  
Fast Transient Response ◽  
Low Dropout Regulator

In this paper, we propose a fully integrated switched-capacitor DC–DC converter with low ripple and fast transient response for portable low-power electronic devices. The proposed converter reduces the output ripple by filtering the control ripple via combining a low-dropout regulator with a main switched-capacitor DC–DC converter with a four-bit digital capacitance modulation control. In addition, the four-phase interleaved technique applied to the main converter reduces the switching ripple. The proposed converter provides an output voltage ranging from 1.2 to 1.5 V from a 3.3 V supply. Its peak efficiency reaches 73% with ripple voltages below 55 mV over the entire output power range. The transient response time for a load current variation from 100 μA to 50 mA is measured to be 800 ns. Importantly, the converter chip, which is fabricated using 0.13 μm complementary metal–oxide–semiconductor (CMOS) technology, has a size of 2.04 mm2. We believe that our approach can contribute to advancements in power sources for applications such as wearable electronics and the Internet of Things.

scholarly journals Giant spin signals in chemically functionalized multiwall carbon nanotubes

2020 ◽  
Vol 6 (31) ◽  
pp. eaba5494
Author(s):  
Roméo Bonnet ◽  
Pascal Martin ◽  
Stéphan Suffit ◽  
Philippe Lafarge ◽  
Aurélien Lherbier ◽  
...  
Keyword(s):  
Low Voltage ◽  
Hyperfine Interactions ◽  
Multiwall Carbon Nanotubes ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Multiwall Carbon Nanotube ◽  
Technology Roadmap ◽  
Spin Polarized ◽  
Multiwall Carbon

Transporting quantum information such as the spin information over micrometric or even millimetric distances is a strong requirement for the next-generation electronic circuits such as low-voltage spin-logic devices. This crucial step of transportation remains delicate in nontopologically protected systems because of the volatile nature of spin states. Here, a beneficial combination of different phenomena is used to approach this sought-after milestone for the beyond–Complementary Metal Oxide Semiconductor (CMOS) technology roadmap. First, a strongly spin-polarized charge current is injected using highly spin-polarized hybridized states emerging at the complex ferromagnetic metal/molecule interfaces. Second, the spin information is brought toward the conducting inner shells of a multiwall carbon nanotube used as a confined nanoguide benefiting from both weak spin-orbit and hyperfine interactions. The spin information is finally electrically converted because of a strong magnetoresistive effect. The experimental results are also supported by calculations qualitatively revealing exceptional spin transport properties of this system.

scholarly journals Low Power SAR ADC Design with Digital Background Calibration Algorithm

Symmetry ◽  
2020 ◽  
Vol 12 (11) ◽  
pp. 1757
Author(s):  
Shouping Li ◽  
Jianjun Chen ◽  
Bin Liang ◽  
Yang Guo
Keyword(s):  
Dynamic Range ◽  
Sampling Rate ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Background Calibration ◽  
Digital Background Calibration ◽  
Common Mode Voltage ◽  
Capacitor Mismatch ◽  
Calibration Algorithm

This paper proposed a digital background calibration algorithm with positive and negative symmetry error tolerance to remedy the capacitor mismatch for successive approximation register analog-to-digital converters (SAR ADCs). Compensate for the errors caused by capacitor mismatches and improve the ADC performance. Combination with a tri-level switching scheme based on the common-mode voltage Vcm to achieve capacitor reduction and high switching energy efficiency. The proposed calibration algorithm significantly improves capacitor mismatch without resorting to extensive computation or dedicated circuits. The active area is 0.046 mm2 in 40 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The post-simulation results show the effective number of bits (ENOB) improves from 8.23 bits to 11.36 bits, signal-to-noise-and distortion ratio (SNDR) improves from 51.33 dB to 70.15 dB, respectively, before and after calibration. This improves the spurious-free dynamic range (SFDR) by 24.13 dB, from 61.50 dB up to 85.63 dB. The whole ADC’s power consumption is only 0.3564 mW at sampling rate fs =2 MS/s and Nyquist input frequency, with a figure-of-merit (FOM) 67.8 fJ/conv.-step.

scholarly journals Towards Fully Integrated Portable Sensing Devices for COVID-19 and Future Global Hazards: Recent Advances, Challenges, and Prospects

Micromachines ◽  
2021 ◽  
Vol 12 (8) ◽  
pp. 915
Author(s):  
Tina Shaffaf ◽  
Saghi Forouhi ◽  
Ebrahim Ghafar-Zadeh
Keyword(s):  
Integrated Circuits ◽  
Point Of Care ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Turnaround Time ◽  
Oxide Semiconductor ◽  
Time Duration ◽  
Fully Integrated ◽  
Diagnostic Assays ◽  
Hands On

Since the onset of the coronavirus disease 2019 (COVID-19) pandemic, this fatal disease has been the leading cause of the death of more than 3.9 million people around the world. This tragedy taught us that we should be well-prepared to control the spread of such infectious diseases and prevent future hazards. As a consequence, this pandemic has drawn the attention of many researchers to the development of portable platforms with short hands-on and turnaround time suitable for batch production in urgent pandemic situations such as that of COVID-19. Two main groups of diagnostic assays have been reported for the detection of Severe Acute Respiratory Syndrome Coronavirus 2 (SARS-CoV-2) including nucleic acid-based and protein-based assays. The main focus of this paper is on the latter, which requires a shorter time duration, less skilled technicians, and faces lower contamination. Furthermore, this paper gives an overview of the complementary metal-oxide-semiconductor (CMOS) biosensors, which are potentially useful for implementing point-of-care (PoC) platforms based on such assays. CMOS technology, as a predominant technology for the fabrication of integrated circuits, is a promising candidate for the development of PoC devices by offering the advantages of reliability, accessibility, scalability, low power consumption, and distinct cost.

scholarly journals 1.0 V-0.18 µm CMOS Tunable Low Pass Filters with 73 dB DR for On-Chip Sensing Acquisition Systems

Electronics ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 563
Author(s):  
Jorge Pérez-Bailón ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Power Consumption ◽  
Dynamic Range ◽  
Low Voltage ◽  
Cutoff Frequency ◽  
Cmos Technology ◽  
Active Area ◽  
Current Steering ◽  
Low Pass ◽  
On Chip ◽  
Low Pass Filters

This paper presents a new approach based on the use of a Current Steering (CS) technique for the design of fully integrated Gm–C Low Pass Filters (LPF) with sub-Hz to kHz tunable cut-off frequencies and an enhanced power-area-dynamic range trade-off. The proposed approach has been experimentally validated by two different first-order single-ended LPFs designed in a 0.18 µm CMOS technology powered by a 1.0 V single supply: a folded-OTA based LPF and a mirrored-OTA based LPF. The first one exhibits a constant power consumption of 180 nW at 100 nA bias current with an active area of 0.00135 mm2 and a tunable cutoff frequency that spans over 4 orders of magnitude (~100 mHz–152 Hz @ CL = 50 pF) preserving dynamic figures greater than 78 dB. The second one exhibits a power consumption of 1.75 µW at 500 nA with an active area of 0.0137 mm2 and a tunable cutoff frequency that spans over 5 orders of magnitude (~80 mHz–~1.2 kHz @ CL = 50 pF) preserving a dynamic range greater than 73 dB. Compared with previously reported filters, this proposal is a competitive solution while satisfying the low-voltage low-power on-chip constraints, becoming a preferable choice for general-purpose reconfigurable front-end sensor interfaces.

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