scholarly journals Giant spin signals in chemically functionalized multiwall carbon nanotubes

2020 ◽  
Vol 6 (31) ◽  
pp. eaba5494
Author(s):  
Roméo Bonnet ◽  
Pascal Martin ◽  
Stéphan Suffit ◽  
Philippe Lafarge ◽  
Aurélien Lherbier ◽  
...  
Keyword(s):  
Low Voltage ◽  
Hyperfine Interactions ◽  
Multiwall Carbon Nanotubes ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Multiwall Carbon Nanotube ◽  
Technology Roadmap ◽  
Spin Polarized ◽  
Multiwall Carbon

Transporting quantum information such as the spin information over micrometric or even millimetric distances is a strong requirement for the next-generation electronic circuits such as low-voltage spin-logic devices. This crucial step of transportation remains delicate in nontopologically protected systems because of the volatile nature of spin states. Here, a beneficial combination of different phenomena is used to approach this sought-after milestone for the beyond–Complementary Metal Oxide Semiconductor (CMOS) technology roadmap. First, a strongly spin-polarized charge current is injected using highly spin-polarized hybridized states emerging at the complex ferromagnetic metal/molecule interfaces. Second, the spin information is brought toward the conducting inner shells of a multiwall carbon nanotube used as a confined nanoguide benefiting from both weak spin-orbit and hyperfine interactions. The spin information is finally electrically converted because of a strong magnetoresistive effect. The experimental results are also supported by calculations qualitatively revealing exceptional spin transport properties of this system.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

A 31 GHz body-biased configurable power amplifier in 28 nm FD-SOI CMOS for 5 G applications

2020 ◽  
pp. 1-18
Author(s):  
Florent Torres ◽  
Eric Kerhervé ◽  
Andreia Cathelin ◽  
Magali De Matos
Keyword(s):  
Power Amplifier ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Fully Depleted ◽  
Technology Roadmap ◽  
Wide Range ◽  
28 Nm ◽  
Soi Cmos

Abstract This paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.

scholarly journals A Fully-Integrated 180 nm CMOS 1.2 V Low-Dropout Regulator for Low-Power Portable Applications

Electronics ◽  
2021 ◽  
Vol 10 (17) ◽  
pp. 2108
Author(s):  
Jorge Pérez-Bailón ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Low Voltage ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
High Gain ◽  
Oxide Semiconductor ◽  
Fully Integrated ◽  
Low Voltage Operation ◽  
Error Amplifier ◽  
Ldo Regulator

This paper presents the design and postlayout simulation results of a capacitor-less low dropout (LDO) regulator fully integrated in a low-cost standard 180 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology which regulates the output voltage at 1.2 V from a 3.3 to 1.3 V battery over a –40 to 120°C temperature range. To meet with the constraints of system-on-chip (SoC) battery-operated devices, ultralow power (Iq = 8.6 µA) and minimum area consumption (0.109 mm2) are maintained, including a reference voltage Vref = 0.4 V. It uses a high-gain dynamically biased folded-based error amplifier topology optimized for low-voltage operation that achieves an enhanced regulation-fast transient performance trade-off.

Complementary metal oxide semiconductor compatible high-voltage transistors

1987 ◽  
Vol 65 (8) ◽  
pp. 1003-1008
Author(s):  
P. Kempf ◽  
R. Hadaway ◽  
J. Kolk
Keyword(s):  
Metal Oxide ◽  
High Voltage ◽  
Process Model ◽  
Low Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Electrical Measurements ◽  
Cmos Transistors

The purpose of this work was to study the implementation of high-voltage transistors using standard 3–5 μm complementary metal oxide semiconductor (CMOS) technology with a minimum of additional photolithographic or implant steps. A fabrication process was designed to accommodate a variety of high-voltage transistors with greater than 450 V breakdown voltage and low-voltage CMOS. Extensive use was made of a two-dimensional device model and a one-dimensional process model to determine suitable process parameters. The necessary conditions to produce a high-voltage double-diffused metal oxide semiconductor (DMOS) structure, as well as both n-well and p-well regions for CMOS transistors, and a thick gate oxide required to sustain the full blocking voltage were the main determinants of the process flow. Lateral DMOS (LDMOS), vertical DMOS (VDMOS), conductivity modulated FET (COMFET), and MOS triac (TRIMOS) devices were fabricated on the same chip as standard CMOS transistors using the developed fabrication sequence. This paper includes the results of the process modelling, device design, and electrical measurements.

scholarly journals State of the Art and Future Perspectives in Advanced CMOS Technology

Nanomaterials ◽  
2020 ◽  
Vol 10 (8) ◽  
pp. 1555 ◽  
Author(s):  
Henry H. Radamson ◽  
Huilong Zhu ◽  
Zhenhua Wu ◽  
Xiaobin He ◽  
Hongxiao Lin ◽  
...  
Keyword(s):  
Semiconductor Industry ◽  
3D Structure ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Strain Engineering ◽  
Oxide Semiconductor ◽  
Process Technology ◽  
Technology Roadmap ◽  
Innovative Methods ◽  
Device Processing

The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

A Low-Voltage and Label-Free Impedance-Based Miniaturized CMOS Biosensor for DNA Detection

2014 ◽  
Vol 67 (1) ◽  
Author(s):  
Vinny Lam Siu Fan ◽  
Wong How Hwan ◽  
Yusmeeraz Yusof
Keyword(s):  
Dynamic Range ◽  
Low Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Label Free ◽  
Fully Integrated ◽  
Technology Process ◽  
Common Gate ◽  
Study Designs

This study designs a low-voltage, label-free and fully integrated impedance-based biosensor using standard complementary metal oxide semiconductor (CMOS) technology to compute both capacitance and resistance of the electrode-electrolyte interface. The proposed biosensor circuit is composed of a common-gate transimpedance amplifier (CG-TIA) with two quadrature phase Gilbert cell double-balanced mixers and finally integrated with microelectrode using 0.18 µm Silterra CMOS technology process. The output value of the readout circuit was used to estimate the magnitude and phase of the measured admittance. The developed CG-TIA can achieve a gain of 88.6 dB up to a frequency of 50 MHz. The overall dynamic range was approximately 116 dB. 

Computational study of the staircase molecular conductivity of polyoxovanadates adsorbed on Au(111)

2021 ◽  
Vol 50 (16) ◽  
pp. 5540-5551
Author(s):  
Almudena Notario-Estévez ◽  
Xavier López ◽  
Coen de Graaf
Keyword(s):  
Metal Oxide ◽  
Computational Study ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Molecular Conduction ◽  
Conduction Properties ◽  
Molecular Conductivity

This computational study presents the molecular conduction properties of polyoxovanadates V6O19 (Lindqvist-type) and V18O42, as possible successors of the materials currently in use in complementary metal–oxide semiconductor (CMOS) technology.

Deep-Submicron Single-Gate Complementary Metal Oxide Semiconductor (CMOS) Technology Using Channel Preamorphization

1998 ◽  
Vol 37 (Part 1, No. 3B) ◽  
pp. 1050-1053 ◽  
Author(s):  
Masayasu Miyake ◽  
Toshio Kobayashi ◽  
Yutaka Sakakibara ◽  
Kimiyoshi Deguchi ◽  
Mitsutoshi Takahashi
Keyword(s):  
Metal Oxide ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor

A 60 GHz reconfigurable active phase shifter based on a vector modulator in 65 nm CMOS technology

2016 ◽  
Vol 8 (3) ◽  
pp. 399-404 ◽  
Author(s):  
Boris Moret ◽  
Nathalie Deltimple ◽  
Eric Kerhervé ◽  
Baudouin Martineau ◽  
Didier Belot
Keyword(s):  
Phase Shift ◽  
Phase Shifter ◽  
Complementary Metal Oxide Semiconductor ◽  
Active Phase ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
60 Ghz ◽  
Semiconductor Technology ◽  
Vector Modulator ◽  
Active Phase Shifter

This paper presents a 60 GHz reconfigurable active phase shifter based on a vector modulator implemented in 65 nm complementary metal–oxide–semiconductor technology. This circuit is based on the recombination of two differential paths in quadrature. The proposed vector modulator allows us to generate a phase shift between 0° and 360°. The voltage gain varies between −13 and −9 dB in function of the phase shift generated with a static consumption between 26 and 63 mW depending on its configuration.

Plain para-aramid/phenolic multiwall carbon nanotubes prepreg/multistiched preform composites: Experimental characterization of mode-I toughness

2018 ◽  
Vol 53 (13) ◽  
pp. 1847-1864 ◽  
Author(s):  
K Bilisik ◽  
E Sapanci
Keyword(s):  
Fracture Toughness ◽  
Multiwall Carbon Nanotubes ◽  
Beam Theory ◽  
Mode I ◽  
Multiwall Carbon Nanotube ◽  
Axial Filament ◽  
Pull Out ◽  
Fiber Bridging ◽  
Nanotube Composites ◽  
Multiwall Carbon

The fracture toughness (mode-I) properties of nanostitched para-aramid/phenolic multiwall carbon nanotube prepreg composites were investigated. The fracture toughness (GIC) of the stitching and nanostitched composites showed 42-fold and 41-fold (beam theory), 18-fold and 21-fold (modified beam theory) increase compared to the control, respectively. The prepreg para-aramid stitching yarn and nanostitched yarn were dominant parameters. The toughness resistance to arrest crack growth in the nanostitched composite was primarily due to nanostitching fiber bridging and pull-out, and was secondarily due to nanotubes and biaxial fiber bridging and pull-out. The failed surfaces of the nanostitched and stitching composites had tensile filament failures in the aramid stitching fibers where filament/matrix/nanotube debonding and axial filament fibrillar splitting were found. The results indicated that stitching yarn and the nanotubes arrested the crack propagation. Therefore, the nanostitched and stitched para-aramid/phenolic composites displayed a better damage resistance performance compared to those of the control or nanotube composites.

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