Analysis of Solder Paste Release in Fine Pitch Stencil Printing Processes

1999 ◽  
Vol 121 (3) ◽  
pp. 169-178 ◽  
Author(s):  
G. Rodriguez ◽  
D. F. Baldwin
Keyword(s):  
High Speed ◽  
Flip Chip ◽  
Imaging System ◽  
Main Process ◽  
Print Quality ◽  
Solder Paste ◽  
Release Process ◽  
Stencil Printing ◽  
Fine Pitch ◽  
Analytical Approaches

Advanced electronics packaging technologies such as chip scale packages, fine pitch ball grid arrays, and flip chip are pushing solder paste stencil printing to the limit. In order to achieve solder print deposits of the sizes required for emerging electronic packaging technology, a rigorous understanding of the process is required. This paper seeks to expand our understanding of the physical characteristics of stencil printing specifically focusing on the solder paste release process based on experimental and analytical approaches. First, designed experiments were conducted to identify the main process variables affecting final print quality. An in-situ measurement system using a high speed imaging system monitored the solder paste release process. Based on experimental observations, different modes of solder paste release and their corresponding mechanisms were identified. A model was developed to predict print quality for fine pitch applications. The proposed model was experimentally verified showing good agreement with measured values for fine pitch and very fine pitch printing. It was found that the cohesive and adhesive forces acting on the paste tend to govern the release process rather than the viscous and inertial forces.

A Study of the Aperture Filling Process in Solder Paste Stencil Printing

1999 ◽  
Author(s):  
Jianbiao Pan ◽  
Gregory L. Tonkay
Keyword(s):  
Flip Chip ◽  
Deposition Process ◽  
Area Ratio ◽  
Solder Paste ◽  
Stencil Printing ◽  
Printing Process ◽  
Surface Mount ◽  
Fine Pitch ◽  
Main Indicator ◽  
Advanced Packaging

Abstract Stencil printing has been the dominant method of solder deposition in surface mount assembly. With the development of advanced packaging technologies such as ball grid array (BGA) and flip chip on board (FCOB), stencil printing will continue to play an important role. However, the stencil printing process is not completely understood because 52–71 percent of fine and ultra-fine pitch surface mount assembly defects are printing process related (Clouthier, 1999). This paper proposes an analytical model of the solder paste deposition process during stencil printing. The model derives the relationship between the transfer ratio and the area ratio. The area ratio is recommended as a main indicator for determining the maximum stencil thickness. This model explains two experimental phenomena. One is that increasing stencil thickness does not necessarily lead to thicker deposits. The other is that perpendicular apertures print thicker than parallel apertures.

Ultra-Thin, Fine-Pitch Step Stencils For Miniature Component Assembly

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-18
Author(s):  
Phani Vallabhajosyula
Keyword(s):  
Visual Inspection ◽  
Flip Chip ◽  
Print Quality ◽  
Solder Paste ◽  
3D Measurement ◽  
Aperture Size ◽  
Fine Pitch ◽  
Technology Applications ◽  
Component Assembly ◽  
Special Step

Mixed technology applications for Flip-Chip (FC) / SMT require special step stencil designs where flux is printed first for the FC and SMD paste printed next with a second stencil that has a relief pocket etched or formed in the FC area. Step stencils are used when varying stencil thicknesses are required to print into cavities or on elevated surfaces or to provide relief for certain features on a board. In the early days of SMT assembly, Step Stencils were used to reduce the stencil thickness for 25 mil pitch leaded device apertures. Thick metal stencils that have both relief-etch pockets and reservoir step pockets are very useful for paste reservoir printing. However as SMT requirements became more complex and consequently more demanding so did the requirements for complex Step Stencils. Electroform Step-Up Stencils for ceramic BGA's and RF Shields are a good solution to achieve additional solder paste height on the pads of these components as well as providing exceptional paste transfer for smaller components like uBGAs and 0201s. As the components are getting smaller, for example 0201m, or as the available real estate for component placement on a board is getting smaller – finer is the aperture size and pitch on the stencils. Aggressive distances from step wall to aperture are also required. Ultra-thin stencils with thicknesses in the order of 40um with steps of 13um are used to obtain desired print volume. These applications and the associated stencil design to achieve a solution will be discussed in detail in this paper. Various print experiments will be conducted and print quality will be determined by visual inspection and 3D measurement of the paste deposit to understand the volume transfer efficiency.

Electrolytic Solder Deposit for Next Generation Flip Chip Solder Bumping

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000671-000707
Author(s):  
Stephen Kenny ◽  
Sven Lamprecht ◽  
Kai Matejat ◽  
Bernd Roelfs
Keyword(s):  
Flip Chip ◽  
Practical Experience ◽  
Electrolytic Deposition ◽  
Solder Paste ◽  
Stencil Printing ◽  
Printing Process ◽  
Advantages And Disadvantages ◽  
Novel Approach ◽  
Solder Bumps ◽  
Chip Attachment

Electrolytic Solder Deposit for Current methods for the formation of pre-solder bumps for flip chip attachment use stencil printing techniques with an appropriate solder paste. The continuing trend towards increasing miniaturisation and the associated decrease in size of solder resist opening, SRO is causing production difficulties with the stencil printing process. Practical experience of production yields has shown that stencil printing will not be able to meet future requirements for solder bump pitch production below 0.15 mm for these applications. This paper describes a novel approach to replace the stencil printing process by use of an electrolytic deposition of solder. In contrast to stencil printing, use of electrolytic deposition techniques allows production of solder bumps with a pitch below 0.15 mm and with a SRO below 80 μm. Methods for production of electrolytic solder bumps based on pure tin as well as alloys of tin/copper and also tin/silver are shown and in particular a method to control the alloy concentration of electroplated tin/copper bumps. Test results with both alloy systems and also pure tin bumping are presented together with comparison of the advantages and disadvantages. The general advantages of replacement of stencil printing by electrolytic deposition of solder bumps are shown and in particular the improvement of bump reliability and the potential to significantly decrease costs by yield improvement.

Control of Bump Morphology in Lead Free Solder Plating for Higher Density Packaging

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001643-001669
Author(s):  
Koji Tatsumi ◽  
Kyouhei Mineo ◽  
Takeshi Hatta ◽  
Takuma Katase ◽  
Masayuki Ishikawa ◽  
...  
Keyword(s):  
High Speed ◽  
Flip Chip ◽  
New Technologies ◽  
Short Circuit ◽  
Lead Free Solder ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Different Shapes ◽  
Free Solder ◽  
High Density Packaging

Solder bumping is one of the key technologies for flip chip connection. Flip chip connection has been moving forward to its further downsizing and higher integration with new technologies, such as Cu pillar, micro bump and Through Silicon Via (TSV). Unlike some methods like solder printing and ball mounting, electroplating is a very promising technology for upcoming finer bump formation. We have been developing SnAg plating chemical while taking technology progress and customers' needs into consideration at the same time. Today, we see more variety of requests including for high speed plating to increase the productivity and also for high density packaging such as narrowing the bump pitch itself and downsizing of the bump diameter. To meet these technical needs, some adjustments of plating chemical will be necessary. This time we developed new plating chemicals to correspond to bump miniaturization. For instance, our new SnAg chemical can control bump morphology while maintaining the high deposition speed. With our new plating chemicals, we can deposit mushroom bumps that grow vertically against the resist surface, also this new chemicals work effectively to prevent short-circuit between mushroom bumps with fine pitch from forming. In addition, we succeeded in developing high speed Cu pillar plating chemicals that can control the surface morphology to create different shapes. We'd like to present our updates on controlling bump morphology for various applications.

Determination of Shear Stress at a Solder Paste/Stencil Interface

1993 ◽  
Vol 323 ◽  
Author(s):  
Linda M. Head ◽  
Vincent Rogers ◽  
Chitteranjan Sahay ◽  
James Constable
Keyword(s):  
Shear Stress ◽  
Mechanical Test ◽  
Test Procedure ◽  
Shear Thinning ◽  
Solder Paste ◽  
Parallel Plates ◽  
Release Process ◽  
Stencil Printing ◽  
Plate Separation ◽  
Lift Off

AbstractTo create a model for the release process of solder paste during stencil printing for surface mount applications it is necessary to determine the shear stress developed at the interface between the solder paste and stencil sidewall. An experiment has been developed to determine the value of the shear stress for solder paste samples. For the purpose of this experiment a Micro-mechanical tester has been adapted and programmed to provide both a shear thinning cycle and a pull-off cycle that simulate aperture fill and stencil lift-off. The shear stress developed at the solder/stencil-sidewall interface is estimated from the data obtained during the pull-off portion of the Micro-mechanical test procedure. The micro-mechanical tester is fitted with a set of parallel plates that can be adjusted for plate separation and surface roughness.The experiment consists of two parts: (1) the shear thinning cycle and (2) the horizontal pull-off. After application of the solder paste and adjustment of plate separation, a back and forth movement of the upper plate provides shear thinning of the paste. This step is necessary to simulate the shear thinning that occurs from the application of squeege pressure during aperture fill. The horizontal pull-off then simulates the lift-off step of the stencil printing procedure. During the horizontal pull-off data is. taken which allows calculation of the force developed as the upper plate is pulled away from the lower. Results from this experiment show the values of shear stress that develop during pull-off with a variation of surface treatments and plate separations.This paper will present the experimental set-up, a description of the relationship between this experiment and the actual stencil lift-off process, and shear stress data that has been acquired for a variety of solder pastes and plate separations.

Cu Pillar Bumping Technology with Solder Alloy Versatility

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002360-002376
Author(s):  
Guy Burgess ◽  
Anthony Curtis ◽  
Tom Nilsson ◽  
Gene Stout ◽  
Theodore G. Tessier
Keyword(s):  
Solder Alloy ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Solder Paste ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Cu Pillar Bump ◽  
Wide Range ◽  
Method Of Production ◽  
Board Level

There is considerable interest in the semiconductor industry regarding Cu pillar bumping for finer pitch flip chip and 3D packaging applications. A common Cu Pillar method of production incorporates a combined Cu plated post topped with a plated solder pillar cap, usually of a Sn or SnAg alloy. Compared with this, a unique method of Cu pillar bump production developed at FlipChip International, LLC (FCI) creates the solder cap by applying and reflowing a solder paste on top of the plated Cu post. This method of production offers several benefits; the most important include a broader solder alloy selection, better alloy control, and improved overall pillar height uniformity. FCI has qualified a wide range of Cu pillar bump sizes, heights and shapes including Cu pillar bumps for fine pitch applications as low as 35um pitch (NANOPillarTM). FCI's Cu pillar bump structures in overmolded SiP have passed JEDEC 22-A104C board level thermal cycle testing, JEDEC J-STD-20A MLS 3@260C, as well as other board level corrosion and shock testing. FCI has demonstrated capping Cu pillar bumps with a broad range of solder alloys tailored to specific application requirements.

Wafer Level Solder Bumping and Flip Chip Assembly with Solder Balls Down to 30μm

2011 ◽  
Vol 2011 (1) ◽  
pp. 000953-000960 ◽  
Author(s):  
Thomas Oppert ◽  
Rainer Dohle ◽  
Jörg Franke ◽  
Stefan Härter
Keyword(s):  
Solder Ball ◽  
Flip Chip ◽  
Temperature Cycling ◽  
Solder Paste ◽  
Wafer Level ◽  
Solder Alloys ◽  
Flip Chips ◽  
Fine Pitch ◽  
Solder Bumps ◽  
Cost Efficient

The most important technology driver in the electronics industry is miniaturization mainly driven by size reduction on wafer level and cost. One of the interconnection technologies for fine pitch applications with the potential for highest integration and cost savings is Flip Chip technology. The commonly used method of generating fine pitch solder bumps is by electroplating the solder. This process is difficult to control or even impossible if it comes to ternary or quaternary alloys. The work described in this study addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping and the use of a very large variety of solder alloys. This flexibility in the selection of the solder materials and UBM stacks is a large advantage if it is essential to improve temperature cycling resistance, drop test resistance, or to increase electromigration lifetime. The technology allows rapid changeover between different low melting solder alloys. Tighter bump pitches and a better bump quality (no flux entrapment) are achievable than with screen printing of solder paste. Because no solder material is wasted, the material costs for precious metal alloys like Au80Sn20 are much lower than with other bumping processes. Solder bumps with a diameter between to date 30 μm and 500 μm as well as small and large batches can be manufactured with one cost efficient process. To explore this potential, cost-efficient solder bumping and automated assembly technologies for the processing of Flip Chips have been developed and qualified. Flip Chips used in this study are 10 mm by 10 mm in size, have a pitch of 100 μm and a solder ball diameter of 30 μm, 40 μm or 50μm, respectively. Wafer level solder application has been done using wafer level solder sphere transfer process or solder sphere jetting technology, respectively. The latter tool has been used for many years in the wafer level packaging industry for both Flip Chip and chip scale packaging applications. It is commonly known in the industry as a solder ball bumping equipment. For the described work the process was scaled down for processing solder spheres with a diameter of 30 μm what was never done before that way worldwide. The research has shown that the underfill process is one of the most crucial factors when it comes to Flip Chip miniaturization for high reliability applications. Therefore, high performance underfill material was qualified initially [1]. Final long term reliability testing has been done according to MIL-STD883G, method 1010.8, condition B up to thirteen thousand cycles with excellent performance of the highly miniaturized solder joints. SEM/EDX and other analysis techniques will be presented. Additionally, an analysis of the failure mechanism will be given and recommendations for key applications and further miniaturization will be outlined.

The Impact of Stencil Printing Upon Assembly & Reliability Of 0.3mm Pitch CSP Components

2016 ◽  
Vol 2016 (1) ◽  
pp. 000667-000674
Author(s):  
Mark Whitmore ◽  
Jeff Schake
Keyword(s):  
Form Factors ◽  
Preliminary Test ◽  
Process Window ◽  
Solder Paste ◽  
Electronic Assembly ◽  
Stencil Printing ◽  
Printing Process ◽  
Fine Pitch ◽  
Technology Standard ◽  
The Impact

Abstract With the continual shrinking of electronic assembly form factors, designers are being forced towards smaller, more complex components with decreasing interconnection pitches. As a consequence, the Surface Mount assembly process is becoming increasingly challenged. For the stencil printing process, this means that historically accepted stencil aperture area ratio design rules, (which dictate what can or cannot be printed), need to be significantly pushed to extend the printing process for next generation ultra -fine pitch components. As a result, a major study has been undertaken looking at several different aspects of the stencil printing process, and their impact upon the assembly and reliability of 0.3mm pitch CSP components. In a preliminary test, stencil printing factors such as stencil aperture size and printing technology (standard squeegees vs ultrasonically aided active squeegees) were investigated. Data showed that the active squeegees provided a significantly larger process window. Subsequently, components were assembled using a range of solder paste volumes printed with both standard and active squeegee technology. The components assembled using an active squeegee process exhibited higher assembly yield, and also extended reliability when subjected to thermal cycling.

Developments in Stencil Printing Technology for 0.3mm Pitch CSP Assembly

2011 ◽  
Vol 2011 (1) ◽  
pp. 000502-000508 ◽  
Author(s):  
Mark Whitmore ◽  
Clive Ashmore
Keyword(s):  
Form Factor ◽  
Area Ratio ◽  
Transfer Efficiency ◽  
Solder Paste ◽  
Assembly Process ◽  
Next Generation ◽  
Stencil Printing ◽  
Printing Process ◽  
Fine Pitch ◽  
Solder Pastes

As electronics assemblies continue to shrink in form factor, forcing designers towards smaller components with decreasing pitches, the Surface Mount assembly process is becoming increasingly challenged. A new “active” squeegee printing process has been developed to assist in the stencil printing of solder pastes for next generation ultra fine pitch components such as 0.3mm pitch CSP’s. Results indicate that today’s accepted stencil area ratio rules, which govern solder paste transfer efficiency can be significantly pushed to extend stencil printing process capabilities to stencil apertures having area ratios as low as 0.4. Such a breakthrough will allow the printing of ultra fine pitch components and additionally will assist with heterogeneous assembly concerns, to satisfy up and coming mixed technology demands.

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