The Impact of Stencil Printing Upon Assembly & Reliability Of 0.3mm Pitch CSP Components

2016 ◽  
Vol 2016 (1) ◽  
pp. 000667-000674
Author(s):  
Mark Whitmore ◽  
Jeff Schake
Keyword(s):  
Form Factors ◽  
Preliminary Test ◽  
Process Window ◽  
Solder Paste ◽  
Electronic Assembly ◽  
Stencil Printing ◽  
Printing Process ◽  
Fine Pitch ◽  
Technology Standard ◽  
The Impact

Abstract With the continual shrinking of electronic assembly form factors, designers are being forced towards smaller, more complex components with decreasing interconnection pitches. As a consequence, the Surface Mount assembly process is becoming increasingly challenged. For the stencil printing process, this means that historically accepted stencil aperture area ratio design rules, (which dictate what can or cannot be printed), need to be significantly pushed to extend the printing process for next generation ultra -fine pitch components. As a result, a major study has been undertaken looking at several different aspects of the stencil printing process, and their impact upon the assembly and reliability of 0.3mm pitch CSP components. In a preliminary test, stencil printing factors such as stencil aperture size and printing technology (standard squeegees vs ultrasonically aided active squeegees) were investigated. Data showed that the active squeegees provided a significantly larger process window. Subsequently, components were assembled using a range of solder paste volumes printed with both standard and active squeegee technology. The components assembled using an active squeegee process exhibited higher assembly yield, and also extended reliability when subjected to thermal cycling.

A Study of the Aperture Filling Process in Solder Paste Stencil Printing

1999 ◽  
Author(s):  
Jianbiao Pan ◽  
Gregory L. Tonkay
Keyword(s):  
Flip Chip ◽  
Deposition Process ◽  
Area Ratio ◽  
Solder Paste ◽  
Stencil Printing ◽  
Printing Process ◽  
Surface Mount ◽  
Fine Pitch ◽  
Main Indicator ◽  
Advanced Packaging

Abstract Stencil printing has been the dominant method of solder deposition in surface mount assembly. With the development of advanced packaging technologies such as ball grid array (BGA) and flip chip on board (FCOB), stencil printing will continue to play an important role. However, the stencil printing process is not completely understood because 52–71 percent of fine and ultra-fine pitch surface mount assembly defects are printing process related (Clouthier, 1999). This paper proposes an analytical model of the solder paste deposition process during stencil printing. The model derives the relationship between the transfer ratio and the area ratio. The area ratio is recommended as a main indicator for determining the maximum stencil thickness. This model explains two experimental phenomena. One is that increasing stencil thickness does not necessarily lead to thicker deposits. The other is that perpendicular apertures print thicker than parallel apertures.

Developments in Stencil Printing Technology for 0.3mm Pitch CSP Assembly

2011 ◽  
Vol 2011 (1) ◽  
pp. 000502-000508 ◽  
Author(s):  
Mark Whitmore ◽  
Clive Ashmore
Keyword(s):  
Form Factor ◽  
Area Ratio ◽  
Transfer Efficiency ◽  
Solder Paste ◽  
Assembly Process ◽  
Next Generation ◽  
Stencil Printing ◽  
Printing Process ◽  
Fine Pitch ◽  
Solder Pastes

As electronics assemblies continue to shrink in form factor, forcing designers towards smaller components with decreasing pitches, the Surface Mount assembly process is becoming increasingly challenged. A new “active” squeegee printing process has been developed to assist in the stencil printing of solder pastes for next generation ultra fine pitch components such as 0.3mm pitch CSP’s. Results indicate that today’s accepted stencil area ratio rules, which govern solder paste transfer efficiency can be significantly pushed to extend stencil printing process capabilities to stencil apertures having area ratios as low as 0.4. Such a breakthrough will allow the printing of ultra fine pitch components and additionally will assist with heterogeneous assembly concerns, to satisfy up and coming mixed technology demands.

Stencil Printing Process Guidelines for 0.3mm Pitch Chip Scale Packages

2013 ◽  
Vol 2013 (1) ◽  
pp. 000569-000573
Author(s):  
Mark Whitmore ◽  
Jeff Schake ◽  
Clive Ashmore
Keyword(s):  
Form Factor ◽  
Area Ratio ◽  
Solder Paste ◽  
Assembly Process ◽  
Aperture Size ◽  
Stencil Printing ◽  
Printing Process ◽  
Fine Pitch ◽  
New Process ◽  
Electronic Assemblies

With the form factor of electronic assemblies continuing to shrink, designers are being forced towards smaller, more complex components with decreasing interconnection pitches. As a consequence, the Surface Mount assembly process is becoming increasingly challenged. For the stencil printing process, todays accepted stencil area ratio rules, (which dictate what can or cannot be printed), need to be significantly pushed to extend the printing process for next generation ultra -fine pitch components. With aperture geometries shrinking, anything which can influence solder paste transfer efficiency has to be considered. New process technologies such as ultrasonic squeegees have emerged in recent years to assist the process with some degree of success. However, something which is often overlooked in terms of stencil design influence is that a square shaped aperture, size for size, has a volume which is 21.5% than its circular counterpart. In a process where quite literally every solder particle that can be printed is becoming significant then this fact can be utilized to the process engineer's advantage. In this paper, the merits of stencil aperture shape, in conjunction with ultrasonic squeegees are investigated with the purpose of developing stencil printing guidelines for ultra-fine pitch components such as 0.3mm pitch CSP's.

Optimal SMT Electronics Assembly Guidelines for Stencil Printing

2015 ◽  
Vol 2015 (1) ◽  
pp. 000126-000134
Author(s):  
Ed Briggs
Keyword(s):  
Process Window ◽  
Solder Paste ◽  
Active Components ◽  
Electronics Assembly ◽  
Stencil Printing ◽  
Printing Process ◽  
Chip Scale Package ◽  
Solder Balls ◽  
To Come ◽  
Set Up

The continuing miniaturization of personal electronics devices, such as mobile phones, personal music devices, and personal computing devices has driven the need for increasingly smaller active and passive electrical components. Not too long ago, 0402 (40 × 20mils) passives were seen as the ultimate in miniaturization, but recently 0201 and now 01005 passives have arrived, with predictions of even smaller sizes to come. For active components, the 30mil CSP (a chip-scale package with the solder balls on 30mil/0.75mm centers) has virtually become a requirement for enabling the many features required in modern portable electronics devices. This miniaturization trend, occurring simultaneously with the conversion to RoHS-compliant lead-free assembly, has put a considerable strain on the electronics assembly industry. This paper will discuss guidelines to optimize the electronics assembly process focusing primarily on stencil printing. With a smaller process window, each variable in the process contributes to the overall success of the assembly. Simple contributions such as storage and handling of solder paste can make or break a printing process. Many solder defects (some say 60–70%) can be attributed to the printing process. Therefore, stencil printing set-up is discussed, as well as solder paste measurement metrics, to determine the potential for success and assure a reliable solder joint.

scholarly journals Eco-Friendly Lead-Free Solder Paste Printing via Laser-Induced Forward Transfer for the Assembly of Ultra-Fine Pitch Electronic Components

Materials ◽  
2021 ◽  
Vol 14 (12) ◽  
pp. 3353
Author(s):  
Marina Makrygianni ◽  
Filimon Zacharatos ◽  
Kostas Andritsos ◽  
Ioannis Theodorakos ◽  
Dimitris Reppas ◽  
...  
Keyword(s):  
High Resolution ◽  
Form Factors ◽  
Circuit Board ◽  
Lead Free ◽  
Process Conditions ◽  
Solder Paste ◽  
Electronic Components ◽  
Successful Operation ◽  
Fine Pitch ◽  
Forward Transfer

Current challenges in printed circuit board (PCB) assembly require high-resolution deposition of ultra-fine pitch components (<0.3 mm and <60 μm respectively), high throughput and compatibility with flexible substrates, which are poorly met by the conventional deposition techniques (e.g., stencil printing). Laser-Induced Forward Transfer (LIFT) constitutes an excellent alternative for assembly of electronic components: it is fully compatible with lead-free soldering materials and offers high-resolution printing of solder paste bumps (<60 μm) and throughput (up to 10,000 pads/s). In this work, the laser-process conditions which allow control over the transfer of solder paste bumps and arrays, with form factors in line with the features of fine pitch PCBs, are investigated. The study of solder paste as a function of donor/receiver gap confirmed that controllable printing of bumps containing many microparticles is feasible for a gap < 100 μm from a donor layer thickness set at 100 and 150 μm. The transfer of solder bumps with resolution < 100 μm and solder micropatterns on different substrates, including PCB and silver pads, have been achieved. Finally, the successful operation of a LED interconnected to a pin connector bonded to a laser-printed solder micro-pattern was demonstrated.

Electrolytic Solder Deposit for Next Generation Flip Chip Solder Bumping

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000671-000707
Author(s):  
Stephen Kenny ◽  
Sven Lamprecht ◽  
Kai Matejat ◽  
Bernd Roelfs
Keyword(s):  
Flip Chip ◽  
Practical Experience ◽  
Electrolytic Deposition ◽  
Solder Paste ◽  
Stencil Printing ◽  
Printing Process ◽  
Advantages And Disadvantages ◽  
Novel Approach ◽  
Solder Bumps ◽  
Chip Attachment

Electrolytic Solder Deposit for Current methods for the formation of pre-solder bumps for flip chip attachment use stencil printing techniques with an appropriate solder paste. The continuing trend towards increasing miniaturisation and the associated decrease in size of solder resist opening, SRO is causing production difficulties with the stencil printing process. Practical experience of production yields has shown that stencil printing will not be able to meet future requirements for solder bump pitch production below 0.15 mm for these applications. This paper describes a novel approach to replace the stencil printing process by use of an electrolytic deposition of solder. In contrast to stencil printing, use of electrolytic deposition techniques allows production of solder bumps with a pitch below 0.15 mm and with a SRO below 80 μm. Methods for production of electrolytic solder bumps based on pure tin as well as alloys of tin/copper and also tin/silver are shown and in particular a method to control the alloy concentration of electroplated tin/copper bumps. Test results with both alloy systems and also pure tin bumping are presented together with comparison of the advantages and disadvantages. The general advantages of replacement of stencil printing by electrolytic deposition of solder bumps are shown and in particular the improvement of bump reliability and the potential to significantly decrease costs by yield improvement.

The behaviour of solder pastes in stencil printing with electropolishing process

2013 ◽  
Vol 25 (3) ◽  
pp. 164-174 ◽  
Author(s):  
Yong‐Won Lee ◽  
Keun‐Soo Kim ◽  
Katsuaki Suganuma
Keyword(s):  
Circuit Board ◽  
Surface Finishing ◽  
Design Parameters ◽  
Solder Paste ◽  
Stencil Printing ◽  
Printing Process ◽  
Content Type ◽  
Solder Paste Printing ◽  
Solder Mask

PurposeThe purpose of this paper is to study the effect of the electropolishing time of stencil manufacturing parameters and solder‐mask definition methods of PCB pad design parameters on the performance of solder paste stencil printing process for the assembly of 01005 chip components.Design/methodology/approachDuring the study, two types of stencils were manufactured for the evaluations: electroformed stencils and electropolished laser‐cut stencils. The electroformed stencils were manufactured using the standard electroforming process and their use in the paste printing process was compared against the use of an electropolished laser‐cut stencil. The electropolishing performance of the laser‐cut stencil was evaluated twice at the following intervals: 100 s and 200 s. The performance of the laser‐cut stencil was also evaluated without electropolishing. An optimized process was established after the polished stencil apertures of the laser‐cut stencil were inspected. The performance evaluations were made by visually inspecting the quality of the post‐surface finishing for the aperture wall and the quality of that post‐surface finishing was further checked using a scanning electron microscope. A test board was used in a series of designed experiments to evaluate the solder paste printing process.FindingsThe results demonstrated that the length of the electropolishing time had a significant effect on the small stencil's aperture quality and the solder paste's stencil printing performance. In this study, the most effective electropolishing time was 100 s for a stencil thickness of 0.08 mm. The deposited solder paste thickness was significantly better for the enhanced laser‐cut stencil with electropolishing compared to the conventional electroformed stencils. In this printing‐focused work, print paste thickness measurements were also found to vary across different solder‐mask definition methods of printed circuit board pad designs with no change in the size of the stencil aperture. The highest paste value transfer consistently occurred with solder‐mask‐defined pads, when an electropolished laser‐cut stencil was used.Originality/valueDue to important improvements in the quality of the electropolished laser‐cut stencil, and based on the results of this experiment, the electropolished laser‐cut stencil is strongly recommended for the solder paste printing of fine‐pitch and miniature components, especially in comparison to the typical laser‐cut stencil. The advantages of implementing a 01005 chip component mass production assembly process include excellent solder paste release, increased solder volume, good manufacture‐ability, fast turnaround time, and greater cost saving opportunities.

scholarly journals Ball Misplace Mitigation through Process Optimization of Advanced Leadframe Package

2020 ◽  
pp. 35-38
Author(s):  
Bryan Christian S. Bacquian ◽  
Frederick Ray I. Gomez ◽  
Edwin M. Graycochea Jr.
Keyword(s):  
Process Optimization ◽  
Parameter Optimization ◽  
Semiconductor Manufacturing ◽  
Manufacturing Industry ◽  
Solder Ball ◽  
Development Phase ◽  
Solder Paste ◽  
Stencil Printing ◽  
Printing Process ◽  
Centered Ball

One of the challenging assembly processes in semiconductor manufacturing industry is stencil printing using solder paste as direct material. With this technology, some issues were encountered during the development phase of an advanced leadframe device and one of which is the solder ball misplace or off-centered ball. This paper, hence, focused on addressing the ball misplace issue at stencil printing process. Comprehensive parameter optimization particularly on the print speed and print force was employed to eliminate or significantly reduce the ball misplace defect at stencil printing process. With this process optimization and improvement, a reduction of around 96 percent ball misplace occurrence was achieved.

A Repeatable and Reliable Rework Process for Lead-Free Fine Pitch BGA’s

2005 ◽  
Author(s):  
Deepak Manjunath ◽  
Satyanarayan Iyer ◽  
Shawn Eckel ◽  
Purushothaman Damodaran ◽  
Krishnaswami Srihari
Keyword(s):  
Primary Objective ◽  
Lead Free ◽  
Process Window ◽  
Solder Paste ◽  
Ball Grid Arrays ◽  
Joint Reliability ◽  
Fine Pitch ◽  
Pros And Cons ◽  
Free Solder ◽  
Rework Process

Fine pitch leadless components, such as Ball Grid Arrays (BGAs) and Chip-Scale Packages (CSPs), are increasingly used in modern day circuitry to aid miniaturization. Assembling these surface mount components using lead-free solder pastes has been a subject of interest for the past several years. Reworking a BGA is complicated as the solder joints are hidden underneath the component. The process window available for the rework process is very narrow and there are number of other critical factors, which complicate and affect the repeatability of the rework process. Consequently, the primary objective of this research endeavor is to develop a reliable and a repeatable process to rework lead-free fine pitch BGAs. The process steps to rework a BGA are component removal, site redressing, solder paste/flux deposition, component replacement and reflow. This experimental study evaluates a number of alternatives for several rework process steps during the course of developing a reliable and repeatable rework process. Two alternatives for site redressing namely, (i) copper wick with soldering iron, and (ii) vacuum de-soldering methods are evaluated. Similarly the application of solder paste versus gel flux is compared. A localized reflow method for replacing the component at the SRT machine is developed and it is compared with forced convection in reflow oven. The pros and cons of using the two reflow methods and the effect of multiple reflows on solder joint reliability is discussed in the paper. A reliability study was conducted on the samples and the results are presented to compare the various alternatives.

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