Lead Free Flip Chip Reliability for Various Package Types

2011 ◽  
Author(s):  
Nokibul Islam ◽  
Miguel Jimarez ◽  
Ahmer Syed ◽  
TaeKyeong Hwang ◽  
JaeYun Gim ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Heat Dissipation ◽  
Coefficient Of Thermal Expansion ◽  
High Reliability ◽  
Large Body ◽  
Temperature Cycle ◽  
Molding Compound ◽  
Board Level ◽  
Board Level Reliability

Flip Chip (FC) technology has now become the mainstream solution for high performance packages. From commercial gaming machines to high reliability servers, the FC package is gaining more market share over traditional packaging technologies, such as wire bond. Extensive research has been carried out to make the flip chip more robust, smaller foot prints, and excellent performance. FC packages are fabricated typically in two main configurations. Bare die FC packages leave the non active side of the die exposed. This allows the customer to apply their preferred heat dissipation scheme during board level attach. Lidded FC packages use a metallic lid attached to the die. Bare die package can be further subdivided into bare die underfilled package and bare die flip chip molded ball grid array (FCmBGA) package. Each of these packaging configurations has advantages as well as disadvantages. FCmBGA uses molding compound or EMC instead of capillary underfill, to protect FC die, and eliminate the need for a lid. Package warpage reduced a lot by adding a lid with the bare die FC package. However, the package and board level reliability for the above package types are still debatable. In this study test vehicles with three package types with bumps and BGAs are daisy chain to measure in situ data during accelerated tests. Impact of standard vs. low CTE (coefficient of thermal expansion) core substrate, accelerated temperature cycle conditions (temperature cycle condition “B”, “H”, and “J” according to JEDEC), and package level vs. package mounted on the board level reliability will be investigated. Comprehensive reliability data will help to select the right package type for next generation large die large body flip chip application.

Mechanical and Thermal Board Level Reliability Comparison Between Electroless Ni Im. Au and Solder on Pad Surface Finishes for Large Flip Chip BGA Packages

2006 ◽  
Author(s):  
Gnyaneshwar Ramakrishna ◽  
Donghyun Kim ◽  
Mudasir Ahamad ◽  
Lavanya Gopalakrishnan ◽  
Mason Hu ◽  
...  
Keyword(s):  
Surface Finish ◽  
Flip Chip ◽  
High Reliability ◽  
Electroless Nickel ◽  
Temperature Cycling ◽  
Design Parameters ◽  
Temperature Cycle ◽  
Bga Packages ◽  
Reliability And Robustness ◽  
Board Level

Large Flip Chip BGA (FCBGA) packages are needed in high pin out applications (>1800), e.g., ASIC's and are typically used in high reliability and robustness applications. Hence understanding the package reliability and robustness becomes one of paramount importance for efficient product design. There are various aspects to the package that need to be understood, to ensure an effective design. The focus of this paper is to understand the BGA reliability of the package with particular reference to comparison of the surface finish, vis-a`-vis, between Electroless Nickel Immersion Gold (ENIG) and Solder On Pad (SOP) on the substrate side of the package, which are the typical solutions for large plastic FC-BGA packages. Tests, which include board level temperature cycling, monotonic bend and shock testing have been conducted to compare the two surface finish options. The results of these tests demonstrate that the mechanical strength of the interface exceeds by a factor of two for the SOP surface finish, while BGA design parameters play a key role in ensuring comparative temperature cycle reliability in comparison with ENIG packages.

High Reliability and Thermal Performance FCBGA Package

2007 ◽  
Author(s):  
Gino Hung ◽  
Ho-Yi Tsai ◽  
Chun An Huang ◽  
Steve Chiu ◽  
C. S. Hsiao
Keyword(s):  
Thermal Performance ◽  
High Performance ◽  
Flip Chip ◽  
Dielectric Material ◽  
High Reliability ◽  
Lead Free ◽  
Molding Process ◽  
Molding Compound ◽  
Reliability Performance ◽  
Low K

A high reliability and high thermal performance molding flip chip ball grid arrays structure which was improved from Terminator FCBGA®. (The structure are shown as Fig. 1) It has many advantages, like better coplanarity, high through put (multi pes for each shut of molding process), low stress, and high thermal performance. In conventional flip chip structure, underfill dispenses and cure processes are a bottleneck due to low through put (dispensing unit by unit). For the high performance demand, large package/die size with more integrated functions needs to meet reliability criteria. Low k dielectric material, lead free bump especially and the package coplanarity are also challenges for package development. Besides, thermal performance is also a key concern with high power device. From simulation and reliability data, this new structure can provide strong bump protection and reach high reliability performance and can be applied for low-K chip and all kind of bump composition such as tin-lead, high lead, and lead free. Comparing to original Terminator FCBGA®, this structure has better thermal performance because the thermal adhesive was added between die and heat spreader instead of epoxy molding compound (EMC). The thermal adhesive has much better thermal conductivity than EMC. Furthermore, this paper also describes the process and reliability validation result.

Low-K Flip Chip Board Level Reliability on 65nm Technology

2007 ◽  
Author(s):  
Pei-Haw Tsao ◽  
Bill Kiang ◽  
Kenneth Wu ◽  
Abel Chang ◽  
Tsorng-Dih Yuan
Keyword(s):  
Flip Chip ◽  
Board Level ◽  
Board Level Reliability ◽  
Low K

Package Qualification Envelope for 22FDX® Technology

2019 ◽  
Vol 2019 (1) ◽  
pp. 000169-000175
Author(s):  
Christian Klewer ◽  
Frank Kuechenmeister ◽  
Jens Paul ◽  
Dirk Breuer ◽  
Bjoern Boehme ◽  
...  
Keyword(s):  
Flip Chip ◽  
Silicon On Insulator ◽  
Wafer Level ◽  
Characterization Methods ◽  
Fully Depleted ◽  
Individual Market ◽  
The Individual ◽  
Key Aspects ◽  
Board Level ◽  
Board Level Reliability

Abstract This article describes the methodology used to derive the 22FDX® Fully-Depleted Silicon-On-Insulator (FDSOI) Chip Package Interaction (CPI) qualification envelope. In the first part it is discussed how the individual market segments influence the technology features and offerings, including BEOL stacks and package types. In the following, the criteria used for the selection of BEOL stacks, die and package sizes and the interconnect type for the qualification envelope are summarized and explained. The three CPI qualification stages and related characterization methods are presented. CPI test structures used in the envelope are reported and their placement on the technology qualification vehicles (TQV) is outlined on the basis of flip chip TQV. Finally, the paper presents the passing 22FDX® package and board level reliability results obtained for wire bond, flip chip, as well as wafer level fan-in and fan-out package technologies. Key aspects of the individual qualifications are reported.

Interactions between Variable Frequency Microwave Underfill Processing and High Performance Packaging Materials

2013 ◽  
Vol 2013 (1) ◽  
pp. 000461-000466 ◽  
Author(s):  
Mamadou Diobet Diop ◽  
Marie-Claude Paquet ◽  
Dominique Drouin ◽  
David Danovitch
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Curing Temperature ◽  
Variable Frequency ◽  
Asymmetric Distribution ◽  
Unexpected Result ◽  
Scanning Calorimetry ◽  
Negative Effect ◽  
Curing Methods

Variable frequency microwave (VFM) has been recently proposed as an alternative underfill curing method that provides flip chip package warpage improvement as well as potential underfill cure time reductions. The current paper outlines how such advantages in VFM processing of underfill can be compromised when applied to high performance organic packages. VFM recipes for three underfill materials were developed by performing several VFM curing runs followed by curing rate measurements using the differential scanning calorimetry method. The VFM curing rate was seen to strongly dependent upon the underfill chemistry. By testing flip chip parts that comprised large and high-end substrates, we showed that the underfill material has negligible impact on VFM warpage with the major cause attributed to the coefficient of thermal expansion mismatch between the die and the substrate. Comparison between the convection and the VFM methods indicated two warpage tendencies that depended upon the VFM curing temperature. First, when both curing methods used comparably high temperatures, warpage increases up to about + 20% were found with VFM. This unexpected result was explained by the high-density Cu loading of the substrate which systematically carried heat generated by VFM energy from the die/underfill system to the substrate. Since this high-end substrate consists of sequential dielectric/Cu layers with asymmetric distribution of Cu, additional stresses due to local CTE mismatches between the Cu and the dielectric layers were induced within the substrate processed with VFM. Second, warpage reductions down to about − 22% were obtained at the VFM curing temperature of 110°C with a curing time similar to that of convection cure. This suggests that the negative effect of the local CTE mismatches were no longer at play at the lower VFM temperatures and that the significantly lower final cure temperatures produced lower total shrinkage of the die and the substrate. Finally, due to lower elastic moduli, the cured VFM parts showed better mechanical reliability with no fails up to 1500 cycles.

Two-Layer Solder Resist Film with Low Young’s Modulus for High Reliability

2020 ◽  
Vol 2020 (1) ◽  
pp. 000307-000312
Author(s):  
YingHsuan Chou ◽  
Daichi Okamoto ◽  
Hidekazu Miyabe
Keyword(s):  
Thermal Resistance ◽  
Crack Resistance ◽  
Young’S Modulus ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Young's Modulus ◽  
Layer Structure ◽  
High Reliability ◽  
Bga Packages ◽  
Link Density

Abstract In this paper, we reveal the development of a novel two-layer Solder Resist (SR) film with low young’s modulus which consists of low young’s modulus layer that possesses excellent adhesion to substrate and thermal resistance layer which is composed of resins with high thermal resistance and great toughness. This novel two-layer SR film exhibits superior resolution and crack resistance. Furthermore, the amount of warpage is extremely low. In general, the material with low young’s modulus and high elongation is caused from weak cross-link density, resulting in poor thermal resistance and delamination which occurs when mounting at high temperature. Herein, we can inhibit delamination successfully by this new two-layer structure film with superior thermal resistance. The Coefficient of Thermal Expansion (CTE) of conventional SR for FC-BGA is 35 ppm, and modulus is 4.5 GPa, whereas, this advanced two-layer SR film exhibits CTE of 66 ppm, and modulus of 2.3 GPa. In order to compare the crack resistance between conventional SR and newly developed two-layer SR film, the film was laminated on BGA substrate (substrate size is 50 mm × 50 mm), patterned by photolithography and cured, and then, 25 mm × 25 mm chip was mounted on a BGA substrate by flip-chip bonder. Conducting thermal cycle test (TCT) and observing the number of cracks after 1000 cycles of TCT. The crack occurrence frequency of the conventional SR is 65 %, whereas that of the new two-layer SR film is 4 %. We proved clearly that high CTE and low young’s modulus demonstrate overwhelmingly high crack resistance. Besides, high resolution of this newly developed two-layer film enabled the formation of SR opening (SRO) as small as 40 μm. From the above results, the newly developed two-layer SR film with low young’s modulus is beneficial for the next generation high-density package, especially for the outermost layer of FC-BGA packages and interposers that require higher reliability.

Board-level reliability of coreless flip chip package assembled on a printed circuit board

2009 ◽  
Author(s):  
Tao-Chih Chang ◽  
Jin-Ye Juang ◽  
Hung-Jen Chang ◽  
Chun-Chih Chuang ◽  
Chau-Jie Zhan ◽  
...  
Keyword(s):  
Flip Chip ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Printed Circuit ◽  
Board Level ◽  
Board Level Reliability

Interface Adhesion and Reliability of Microsystem Packaging

2003 ◽  
Vol 782 ◽  
Author(s):  
Marvin I. Francis ◽  
Kellen Wadach ◽  
Satyajit Walwadkar ◽  
Junghyun Cho
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Dissimilar Materials ◽  
Strain Energy Release ◽  
Interface Adhesion ◽  
Curing Conditions ◽  
Chip Technology ◽  
Solder Balls ◽  
Cte Mismatch

ABSTRACTFlip-chip technology is becoming one of the most promising packaging techniques for high performance packages. Solder balls are used as the connection technique in the flip-chip method and the connections are reinforced by filling in the spacing between the chip and substrate with underfill. The function of the underfill is to reduce the stresses in the solder joints caused by a coefficient of thermal expansion (CTE) mismatch. The presence of polymeric underfill material will, however, make the flip-chip packaging system susceptible to interfacial failure. Thus, the purpose of this study is to examine the interfacial delamination between the dissimilar materials in order to increase the reliability of the flip-chip interconnection method, and to understand the effect of underfill curing conditions on the interface adhesion. In particular, we use a linear elastic fracture mechanics (LEFM) approach to assess interfacial toughness. For this purpose, four-point bending testing is performed to determine a critical strain energy release rate, Gc. In addition, nano-indentation testing equipped with atomic force microscope (AFM) is employed to determine structure and properties of the underfill layer.

Low Profile and Large Size WLCSP in IoT Applications

2019 ◽  
Vol 2019 (1) ◽  
pp. 000327-000332
Author(s):  
Tom Tang ◽  
Kuei Hsiao Kuo ◽  
Victor Lin ◽  
Kelly Chen ◽  
J.Y. Chen ◽  
...  
Keyword(s):  
High Performance ◽  
Wafer Level ◽  
Joint Reliability ◽  
Large Size ◽  
Low Profile ◽  
Chip Scale Package ◽  
Iot Devices ◽  
Small Form Factor ◽  
Board Level ◽  
Board Level Reliability

Abstract Recently, Wafer Level Chip Scale Package (WLCSP) Package is being rapidly adopted in Internet of Things (IoT) and consumer mobile electronics due to its low profile, small form factor and relatively easy assembly process. WLCSP with large die size becomes the trend in fulfilling high performance product demands. However, the solder joint reliability performances of WLCSP is the key challenge and becomes critical as increasing die size, especially the size is larger than 6 × 6 mm2. There is also growing interest in low profile WLCSP packages to less than 300 microns, especially when they are placed in a limited space inside IoT devices. Thin wafers are fragile and must be supported over their full dimensions to prevent cracking and breakage. An increasingly popular approach to thin wafer handling involves grinding and taping thin wafers with in-line machines. A specific carry tape have been also developed for transferring thin wafers after thinning. In this paper, WLCSP board level reliability for both large die size and low profile was studied, a test vehicle used for the large WLCSP package testing has 350um ball pitch and fully populated array. In addition to board level reliability test simulation and data collection, processing challenges were discussed, as well as processing solutions for thin wafer handling.

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